I am designing CSI-2 receiver on Cyclone 10LP device. The data are comming from sensor.
CSI clock is about 350 Mhz, 4 data lanes.
At the data inputs I use altlvds_rx. Due to high data rate, deserialisation factor = 4. Thus PLL is inserted. This causes a problem.
Between packets the CSI bus goes to low power mode, the clock is switched off. Before sending a new packet, the bus restores the clk. But the PLL does not have enough time to lock. So the packet is not received.
Can you suggest some solution for this?
P.S. It is not desirable to disable LP mode in the sensor.
Using LP signals I can determine the mode change events.
I am thinking about using "pfdena" signal to disable input detection during low power mode.
The second thing I am thinking about is using "Switchover". I'll use interanlly generated clock with allmost the same frequency as a "backup" clock.
But I am not sure how fast the pll can switch between close frequencies or lock after pfd is enabled.
I've made some experiments with pdfena and switchover.
1. Switchover. When I switch from one 100 MHz source to another 100 MHz source, the pll locks in ~300ns. Not bad. The disadvantage - I have to know the exact CSI clock and produce the same by additional pll.
2. pfdena. When pdfena is inactive, the PLL frequency slowly changes. The longer inactivity time, the bigger the difference. With inactivity time is 200 us and 100 MHz at the input, the lock time is also ~300ns. The higher input frequency, the shorter lock time.
At this point looks like pll will be locked quick enough. The tests will show.
Is there any time gap between the clock reception and the valid data reception? PLL will take this delta time to get locked and be ready to capture the data when it arrives. Is it configurable in the sensor?
For Cyclone 10 LP, the PLL can take max 1ms to lock to the input.
Seems like you have a mechanism to detect the presence of input clock based on which you are trying to control the pfdena signal.
If that is possible, then you can use that mechanism to control the clkswitch input to switch between two different clock inputs.
Please note that the PLL's two clock inputs need not necessarily be at the same frequency. They can be different as well. Refer: https://www.intel.com/content/www/us/en/programmable/documentation/sxm1481253171919.html#xbq14900681...
Yes, at current settings the time between valid clock and vallid data is about 2 us. The pll is able to lock quick enough if I use pdfena.
When using switchover with two different signals, the lock time is much higher, than between similar frequencies. Thats why I wrote about method's disadvantage.