CYCLONE10GX SERDES clock

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

CYCLONE10GX SERDES clock

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Hello,

CYCLONE10GX. In one bank I have two groups of LVDS inputs to hard SERDES.

I need to clock inputs to one group directly and the other group with 180 degree phase (inverted) shifted fast clock.

Is there a possibility to choose receiver fast clock inversion in cyclone10gx_io_serdes ?

Thanks

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