We use 3 pcs of A10 10AX057H3F34E2SG ( named A, B, C) on one board, with inter-FPGA XCVR links between A&B, and B&C. Every link contains x24 Uni-Direction dataflow, with possibly same datarate. as below:
A -----(XCVR x24)-----> B -----(XCVR x24)-----> C
Question: 10AX057H3F34E2SG only has 24 XCVR channels. Can there TX/RX channels be used Independently? Which means, for A only has its TX working, and C only has its RX working, and B's TX and RX in every single lane will work independtly. Meantime, A's RX will Grounded, C's TX will be floated as they are unused.
Is this design feasible? Any special cautions for hardware and logic design? Not sure, hope some Intel expert could kindly help. Thanks very much!
Thanks, Nathan, very useful. We use Quartus Prime Standard rather than Pro, can we just verify our design in Standard version?