we are testing A10 PCIE FPGA example & PCIE Linux driver ( follow link : https://fpgacloud.intel.com/devstore/platform/18.0.0/Pro/arria-10-pcie-gen3-x8-dma/). After building FPGA example and run test on Linux PC, we found dmesg shows:
as you can see, PCIE message shows " BAR 0xa0000000-0xbfffffff , length 536870912
which means BAR access address space is totally “= 0x20000000 bytes = 536870912 bytes "(512MBytes)
But our FPGA has 1GB DDR4 ,and we want PCIE BAR can read/write the whole 1GB FPGA DDR4 from Host PCIE interface, so how can we do to implement this ? Where to config PCIE BAR to access "1gb" address space in paltform designer ?
Thanks a lot
The PCIe IP will auto-detect the BAR size, can you go to “Base Address Registers” -> “BAR 2” -> Size (bit?)? To confirm it is either 29 bits or 30 bits. I connected 1G DDR with BAR2, and I can get 30 bits size for BAR 2.
If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.