Can I produce 4 MHz from a 10 MHz input?

[Altera_Forum]

Hi All, 

 I have a Cyclone IV board. Can I produce 4 MHz from a 10 MHz input? I am totally new to this field. I can produce 4 MHz using the 50 MHz on-board clock using PLL. But it seems GPIO cannot be used as input for PLL. Thanks in advance.

[Altera_Forum]

Yes, in Cyclone IV a GPIO cannot drive a PLL ... 

With careful design you can build a 4 MHz signal from this 10 MHz clock, but only with a 40/60 duty cycle. Careful as in: if you want to use this 4 MHz as a clock you have to watch out for glitches.

[Altera_Forum]

It's true that PLLs have dedicated clock inputs, these give the best performance, but I was able to assign a GPIO as a PLL input on my Cyclone V (not Cyclone IV) device using the global_clock buffer IP. Maybe this is feasible on the Cyclone IV as well?

[Altera_Forum]

@gj_leeson In the Cyclone IV devices, clock control blocks (clock buffer IP) that have inputs driven by internal logic are not able to drive PLL inputs. In other words there is no way to route the signal from a GPIO pin to the PLL. The PLL can only be driven by the dedicated clock lines.

[Altera_Forum]

See the second page of this PDF: https://www.mikrocontroller.net/attachment/177197/xl33_30.pdf 

 That's a divide by 2.5 digital circuit which could be implemented in an FPGA. 10MHz / 2.5 = 4MHz.  It's not going to be a clean clock, there will be quite a lot of jitter, and it is not 50% duty cycle (gives 40% duty).  It could be usable for many designs so long as you don't need sub-nanosecond accuracy.

[Altera_Forum]

--- Quote Start ---  It's true that PLLs have dedicated clock inputs, these give the best performance, but I was able to assign a GPIO as a PLL input on my Cyclone V (not Cyclone IV) device using the global_clock buffer IP. Maybe this is feasible on the Cyclone IV as well?  --- Quote End ---     Interestingly Cyclone V device handbooks says it's no feasible:   --- Quote Start ---  Internally-generated GCLKs, RCLKs, or PCLKs cannot drive the Cyclone V PLLs. The input clock to the PLL has to come from dedicated clock input pins, PLL-fed GCLKs, or PLL-fed RCLKs.  --- Quote End ---    I guess, the Cyclone III/IV constraint is enforced by the design software on purpose. Dropping it for Cyclone V might be just a bug.

[Altera_Forum]

--- Quote Start ---   I guess, the Cyclone III/IV constraint is enforced by the design software on purpose. Dropping it for Cyclone V might be just a bug.  --- Quote End ---    It's not a software bug at all. In fact it is due to a major difference between the design of the clock routing networks in the CV devices compared with their older family.  If you compare page 4-11 of cyclone v datasheet (https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cv_5v2.pdf) with page 5-11 of the cyclone iv datasheet (https://www.altera.com/en_us/pdfs/literature/hb/cyclone-iv/cyiv-51005.pdf) you can see there is a distinct difference in the clock routing networks of the two devices.  In the Cyclone IV devices, PLLs are fed directly from the CLK[N] dedicated inputs, whilst the GCLK network is fed through a separate mux. As such it is not possible to route back from the global clocks into the PLLs.  Comparatively in the Cyclone V devices, PLLs are fed from multiplexers which can select between the dedicated CLK[N] inputs and the GCLK network. As such any global clock (or periphery and regional clock) can feed directly to the PLL reference clock inputs.