Can cyclone III comes into the user mode if AP config failed?

[Altera_Forum]

Original tille: "Can cyclone III comes into the user mode if AP config failed?" 

 I can't find the EP3C120F780I7N when scan the JTAG chain.  I want to kown what happend when nSTATUS and CONF_DONE be drived low after power up, and the nCONFIG is high(3.3V)? I have read the datasheet, (1) the POR error may result in this, (2) the config error also drives the nSTATUS pin low. POR error? or the config error?  I have test the power voltage of 1.2V, 2.5V and 3.3V, and every config pins, nothing wrong. (MSEL set to AP standard MODE). If the P33 Flash is not the FBGA package (I kown that the TSOP package of INTEL dosen't support 40MHz burst read, but the new 256M/512M P33 devices from Micron may support this), can the cyclone III device release the configuration procedure to user mode? This is the reason that nSTATUS and CONF_DONE be drived low?   If the AP config failed, can the JTAG chain scan the device?  I can't find any DCLK pulse after power up, ... it is the POR error?   /**********************************/ 2013-01-25 In order to test the whole resources quickly, I use NIOS II system integrated with SDRAM controller, but the sdram can't verified, even though I have set the phase and reduce the clock frequency. Then, I find answer from datasheet, espicially the clock and pll section. I find that, I have to use c0 output to the dedicated plll_out pin, and the c1 to c4 could be used for internal logic, I connect c1 to NIOS cpu, c0 with a -?ns phase to the sdram clock, i adjust the phase, all right, that' ok!  Then, I designed a Flow-through SSRAM IP core, and import it to the SOPC system from the comphonent editor tool. Samilar to the sdram, I give an appropriate phase, it running well.  But I have three SDRAM, which clock togethered with an resister pack, and three SSRAM together too. The I/O strength of the EP3C120F780 has only maximum 8mA when using LVTTL mode, when I adjust this clock to 100MHz, it floating high with only 100mv vpp, ... I am on the case!

[Altera_Forum]

The FPGA should always answer on the JTAG pins, even if it failed during the configuration phase. Do you have pull-ups on nSTATUS, CONF_DONE and nCONFIG? 

Do you have power to all the I/O banks, and all the PLL supplies? Can you check the soldering of the FPGA balls?

[Altera_Forum]

I'm not aware of the term "POR error" used anywhere in the Altera documentaion, nor can I read a reasonable meaning into it. What do you mean? 

 If you're referring to a state where POR isn't released, check all power supplies that are monitored by the POR circuit as well as the device soldering, as already suggested by Daixiwen. nCONF held permanently low (with proper pull-up) suggests in fact active POR, also inaccessible JTAG.

[Altera_Forum]

Thank you everyone, I have resolved the problem, that's really cause by the POR error, the solder is really ok! 

 I find that the wire of the VCCA and VCCD_PLL must >20mil emphasized on the datasheet, but the inductor connect the VCC_1V2 and VCC_2V5 to these power pins may a bit thin, I replace it with a thick BEAD or large 0 Ohm resister, then I can find the device EP3C120F780I7 through JTAG, yes this.  The nSTATUS signal, by the way, is a periodic pulse from the scope, I think it is excuting the reconfiguration repeatedly, why? I analyzed the reason, and explain it that the package of the intel P30 flash which I used on this board is a TSOP type, the FPGA can shake hands with it in asynchonize mode, but can't implement the AP config loading, for this TSOP package isdosen't support the synchonize burst read, data loding failure, then it repeat..., but this dosen't prevent the JTAG debug, the JTAG has a higher priority, I think so.  Then, I try to pull-down the ADV signal of the P30 flash to forbid the synchronize mode, I find that the periodic pulse of the nSTATUS disappeared, it keep the high level, the JTAG debug also to use ok.  Next step, I must replace this TSOP package to the new Micron 65nm SBC version, I find it really supports the sync burst read from the new distributed datasheets.   Who known the new Micron 65nm SBC version P33 flash (TSOP package)?  I will share the debug info on this issue, please stay tuned.