This is a board used for many versions, and this question is the first time I met, I can download the .jic file through Usb-blaster ii to the FPGA, and quarus show these meassage which means the configuration is sucessful.
Info (209060): Started Programmer operation at Mon Mar 07 10:44:32 2022
Info (209016): Configuring device index 1
Info (209017): Device 1 contains JTAG ID code 0x02B040DD
Info (209007): Configuration succeeded -- 1 device(s) configured
Info (209018): Device 1 silicon ID is 0x18
Info (209044): Erasing ASP configuration device(s)
Info (209019): Blank-checking device(s)
Info (209023): Programming device(s)
Info (209021): Performing CRC verification on device(s)
Info (209011): Successfully performed operation(s)
Info (209061): Ended Programmer operation at Mon Mar 07 10:58:33 2022
when I power down the board, and power up the board again, FPGA can not load the code from EPCQ128 to my FPGA, I measured the conf_done PIN, it is low, but when i measure it before I power down, it is high, which means the PIN is ok, and i have put a 10KΩ pull up with it, at the same time, nStatus PIN keep toggling with 376us high and 256us low.
If I do not use the code in EPCQ128, and only use .sof through JTAG downloaded, I can run my code correctly, so i think the FPGA is good, but if EPCQ was broken, why the quartus can perform CRC verification correctly?
Thanks and best regards
You mentioned that the flow was worked in the past on the other quartus version. May i know what are the changes u made recently?
Having configuration failure could be due to several issue, you may check our troubleshooting guide for that: