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Can't recognize silicon ID for device 1

Altera_Forum
Honored Contributor II
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I designed FPGA Board using Cyclone V Device and EPCQ512 programming. 

 

When program the device using .sof it loads successful and output is also correct. 

 

But when i try to program using .jic it failed to load the program. 

 

Afterthat, i have replaced EPCQ device with Micron. 

 

In micron device, .jic file loads successful, but the output is wrong (cannot see the actual output). 

 

I have also verified the configuration selection. That is also correct. 

 

Please give me the solution for this device.
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Altera_Forum
Honored Contributor II
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I can't read the text on the images you've posted. However, it looks like it's reporting that it can't recognise one of the devices. Is this the same issue as when it 'works' with the Micron part? 

 

 

--- Quote Start ---  

the output is wrong  

--- Quote End ---  

By this, do you meant the FPGA is not doing what you expect having booted from the EPCQ? 

 

Cheers, 

Alex
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Altera_Forum
Honored Contributor II
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1).jic file is not loading in EPCQ512. 

2) Loaded in Micron device, but not shows correct output. 

 

"Error: Can't recognize silicon ID for device 1. A device ID is different from the JTAG ID. Verify that all cables are securely connected"
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Altera_Forum
Honored Contributor II
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"Error: Can't recognize silicon ID for device 1. A device ID is different from the JTAG ID. Verify that all cables are securely connected" 

 

1).jic file is not loading in EPCQ512. 

2) Loaded in Micron device, but not shows correct output. 

 

Need solution for this older issue.
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Altera_Forum
Honored Contributor II
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Having loaded the Micron device and power cycled the board, does the FPGA's 'CONF_DONE' pin go high? 

 

Cheers, 

Alex
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Altera_Forum
Honored Contributor II
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Missed to tell which Micron flash has been used. 

 

If flash verifies O.K. but configuration isn't accepted by FPGA, either wrong settings in Programming File Conversion Tool or MSEL bits must be expected. Checking for error during configuration load (nSTATUS and CONFIG_DONE signaling, how many bits are read from the flash) is interesting nevertheless.
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Altera_Forum
Honored Contributor II
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There's nothing wrong with the bit of schematic you've posted. Does CONF_DONE go high? 

 

Cheers, 

Alex
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Altera_Forum
Honored Contributor II
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Yes. In this case, how to sort out the issue.?

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Altera_Forum
Honored Contributor II
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If CONF_DONE is going high the FPGA has successfully booted from the serial FLASH device. If the FPGA isn't then doing what you expect then the issue is with your design. You need to start debugging. 

 

If the behaviour is different as compared to when you program it with the .sof then check that you've used the correct .sof when generating your .jic file. 

 

If you have used the right one then detail the behaviour differences for us to consider. 

 

Cheers, 

Alex
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