Can you sovle the CPLD?

[Altera_Forum]

Good afternoon~:)Are there any manipulators in here? 

 OK,let’s go into the subject directly.Now let me describe the questions about counting process of the three way external pulse by used cpld (http://www.kynix.com/detail/668602/cpld21d1914gtdta.html). First,CPLD just counts the first pulse. Every second will have a counting result A[31:0] . Second,CPLD measure the width of second variable width pulse by taking the way of counting.At the same time every pulse will product a result of width counting B[15:0]. Third, the third pulse is similar to the second way,it also products a counting result C[15:0].  Now I need a STM32 to read the A in PLCD every second by using spi and do a zero clearing to it, while reading B and C in the constant time. Questions: Do you have any suggestions or realizable way about this problems?:confused: I’m asking for your advice urgently.  Please accept my appreciation! Thanks a lot!

[Altera_Forum]

What code have you written? What problems are you having? 

Cheers, Alex

[Altera_Forum]

--- Quote Start ---  What code have you written? What problems are you having? Cheers, Alex  --- Quote End ---    Hello~thank you for you reply.My problems: I need a STM32 to read the A in PLCD every second by using spi and do a zero clearing to it, while reading B and C in the constant time.I don't know how to realized it ?Can you?

[Altera_Forum]

1) Implement your pulse counting logic in the FPGA (in verilog or vhdl, as you desire). Your requirements above seem pretty clear. 

2) Implement a SPI interface in the FPGA (again, in your language of choice). A SPI interface is a pretty simple logic implementation. 3) Write a testbench to test your FPGA code functionality (ie, write a SPI master controller and have it read/write your FPGA registers). 4) When you are pretty confident it seems to work, compile and program into an FPGA, and then connect to your CPU board and check it. 5) Go back thru the loop to (1) when things don't seem to work.  Once you have some code written, we can comment on it and help you debug it. But we won't write it for you.

[Altera_Forum]

--- Quote Start ---  1) Implement your pulse counting logic in the FPGA (in verilog or vhdl, as you desire). Your requirements above seem pretty clear. 2) Implement a SPI interface in the FPGA (again, in your language of choice). A SPI interface is a pretty simple logic implementation. 3) Write a testbench to test your FPGA code functionality (ie, write a SPI master controller and have it read/write your FPGA registers). 4) When you are pretty confident it seems to work, compile and program into an FPGA, and then connect to your CPU board and check it. 5) Go back thru the loop to (1) when things don't seem to work.  Once you have some code written, we can comment on it and help you debug it. But we won't write it for you.  --- Quote End ---   Thank you for your guidance! It's very kind of you. I'll try it right now.:)