Cannot merge HSSI Avalon Memory-Mapped interface instances for simplex JESD designs

[cheyert]

When instantiating simplex Rx and Tx JESD cores generated by quartus, and enabling the reconfiguration interfaces, the following placement error shows:

Error (12829): Failed to merge HSSI Avalon Memory-Mapped interface instances "main|devices[0].jesd204_rx_core|main|intel_arria_10.unit|intel_jesd204_core|jesd204_core|jesd204_0|inst_phy|inst_xcvr|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst" and "main|devices[0].jesd204_tx_core|main|intel_arria_10.unit|intel_jesd204_core|jesd204_core|jesd204_0|inst_phy|inst_xcvr|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst" into single Avalon Memory-Mapped Interface.

The error is also described here, albeit for a different IP, but still the error is the same..

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/ip/2020/error-12829---failed-to-merge-hssi-avalon-memory-mapped-interfac.html

Another similar issue is here, which does seem to have a workaround

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd09282014_173.html

So is there a workaround for my case as well, or is upgrading to latest quartus really necessary, and how do I know that this will in fact solve the issue without having to upgrade the entire design?

[CheePin_C_Intel]

Hi,

Thanks for your update. Please allow me some time to further look into this. Just to check with you if your design changing to 1 lane, can the merging successful? Just to help narrowing down if it is related to the number of lanes configured in the IP.

Thank you.

[CheePin_C_Intel]

Hi,

Just would like to follow up with you on this. Thank you.

[CheePin_C_Intel]

Hi,

As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

[cheyert]

Hello,

I would like to keep this open because as to date I have no resolution to this issue yet.

I'm pretty sure I've exhausted all options as mentioned in the discussion, so not sure how to proceed from here on this issue.

[CheePin_C_Intel]

Hi,

Just to check with you if you have had a chance to try with my previous 2 lanes design which mimic your configuration?

Please let me know if there is any concern. Thank you.

Best regards,
Chee Pin

[cheyert]

I'll try to provide feedback on this tomorrow, I compared the design for settings which all seemed correct, but haven't gone though fitting yet, will attempt tomorrow

Thanks