Chip ID Reading using AVST Mailbox IP in Agilex

[linyag]

hi,

    We are debugging the acceleration board of agilex and want to get the chip id of the board. But when adding Mailbox IP to the project, many errors occurred in the synthesis.

Our project cannot add a singtap to read the chip id. The design scheme is to let the Mailbox IP read the chip id and store it in the register.

Error(11176): Alt_sld_fab_0.alt_sld_fab_0: add_instance: Can't create component type altera_config_clock_source_endpoint_tieoff
Error(11176): Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0.sldfabric.clock: sldfabric.clock must be connected to a clock output
Error(11176): Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0.mboxfabric.clk: mboxfabric.clk must be connected to a clock output
Error(11176): Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0.mboxfabric.clk_0: mboxfabric.clk_0 must be connected to a clock output
Error(11176): Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0.sdmnoc.clk: sdmnoc.clk must be connected to a clock output
Error(11176): Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0.sdmbridge.clk: sdmbridge.clk must be connected to a clock output
Error(11176): Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0.sldfabric.conf_reset_out: sldfabric.conf_reset_out must be connected to a reset source
Error(11176): Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0.mboxfabric.reset: mboxfabric.reset must be connected to a reset source
Error(11176): Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0.mboxfabric.reset_0: mboxfabric.reset_0 must be connected to a reset source
Error(11176): Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0.sdmnoc.reset: sdmnoc.reset must be connected to a reset source

What's the workaround for these errors?

thanks

[KellyJialin_Goh]

Hi,

Greetings and welcome to Intel's forum.

We have a design example for chip ID reading using AVST Mailbox IP for your reference. You may use this design example to see if the error is eliminated: https://www.intel.com/content/www/us/en/design-example/763981/intel-agilex-7-fpga-chip-id-reading-using-avst-mailbox-ip.html

Thank you.

Regards,

Kelly Jialin, GOH

[linyag]

Hi,

The reference is exactly this example, the difference is that the Signal Tap will be used in the example, but the signal tap is turned off in our static. Mailbox IP must need a signal tap?

thanks

[KellyJialin_Goh]

Hi,

For using the Mail Box IP, Signal tap has to be running and connected on Quartus. The documentation can be found on how to run signal tap on the left upper corner here for your reference: https://www.intel.com/content/www/us/en/design-example/763981/intel-agilex-7-fpga-chip-id-reading-using-avst-mailbox-ip.html

Hope this clear your doubts.

Thank you.

Regards,

Kelly

[linyag]

Hi,

In the manual of the mailbox, we can’t find that the chip id must be read through the Signal tap.

In addition, there are other ways to read the chip id for the agilex chip (without using the Signal tap, the user logic obtains the chip id like A10)?

thanks

Regards,

linyag

[KellyJialin_Goh]

Hi,

Signal tap is the only way to read chip ID It is used to capture the response obtained from Mailbox Avalon ST IP and then capture the chip ID. We have a video which might be more helpful for you to see the steps to obtain chip ID: https://www.youtube.com/watch?v=4Ng9p0uK9zU

Hope this could help.

Thank you.

[linyag]

Hi,

Video we have learned.In the video, the mailbox ip is not directly connected to the signal tap. Connected with user logic.

Our idea is to read the chip id from the mailbox and write it into the register, and then read it out through the pice. User logic is written by ourselves.this way is not allowed? Must add signal tap to connect?

thanks

[KellyJialin_Goh]

Hi,

You may have a look at this document to have the host IP communicate with the Mailbox Client IP with the input commands from Figure 2 to request chip ID without connecting using signal tap: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-avst-client-ag.pdf

Looking forward to your feedback whether it works from your end.

Thank you.

Regards,

Kelly

[linyag]

Hi,

According to the requirements in the document, there is still a problem after re-verification, which may be related to the static configuration. We are going to check the FIM of agilex

thanks

[KellyJialin_Goh]

Hi,

Any updates from your end whether the information and documents provided was useful to solve your issue?

Thank you.

Regards,

Kelly

[KellyJialin_Goh]

Hi,

Any updates from your end whether the workaround provided was useful to solve the issue?

Thank you.

Regards,

Kelly

[KellyJialin_Goh]

Hi,

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

Thank you.

Regards,

Kelly Jialin, GOH