Clock Frequency Max

[Altera_Forum]

Hi, this may be a stupid question so I ask for your forgiveness in advance: 

I have an application where I have two square wave inputs at 300 MHz; I wish to measure the time delay between the rising edge of both signals. For this I need to know: what is the maximum clock frequency given by the Cyclone V device? And to what extent can this be increased by built in PLLs? And finally what maximum frequency can the board be reliably and safely be operated at?    Many Thanks,  Numi  

[Altera_Forum]

I think the maximum clock rates that can be achieved inside the fpga can be determined from the device's switching characteristics data sheet. You say you want to measure the time delay between 2 rising edges...the resolution you will achieve will be a function of your sampling clock. Without checking the data sheets, I would think that the 300 MHz input frequencies doesn't give you a lot of options in terms of how fast you can run your sampling clock for a desired resolution. 300 MHz is a pretty brisk input rate, especially for a Cyclone 5 part.

[Altera_Forum]

--- Quote Start ---   I have an application where I have two square wave inputs at 300 MHz; I wish to measure the time delay between the rising edge of both signals.   --- Quote End ---   First question; why?  Clarification; if you are expecting to measure the delay between the edges of the two signals, then they must be synchronous. If the signals are synchronous, then chances are you do not need to align the clock edges, you just need to use FIFOs to move data between the common synchronous clock domains.  If you absolutely have to measure the phase delay, then one way is to use a phase-detector. A "simple" phase-detector can be constructed using high-speed (external) XOR gate followed by a low pass filter. The DC output of that filter represents the phase difference between the two clocks. Depending on your application, this may be sufficient.  Cheers, Dave

[Altera_Forum]

The method of xor suggested by Dave should be ok for phase difference. 

Another draconian method to measure absolute delay is to have two FIR filters of same coefficients (just any symmetric set). Then run each FIR on its clock using impulse input. Measure the delay of peaks e.g. in the scope.

[Altera_Forum]

I'm sorry, the input frequencies are maxed at 300 kHz not MHz. I assume I can use the above suggested methods to even greater effect given this change? As for why, because my professor cannot come up with a more creative assignment. Thanks guys!!!

[Altera_Forum]

And the signals have the same period/frequency, identical characteristics in every way except that one leads the other

[Altera_Forum]

--- Quote Start ---   I'm sorry, the input frequencies are maxed at 300 kHz not MHz   --- Quote End ---   Ok, that is a significantly lower frequency :)  How accurately do you need to know the phase difference? A 300kHz waveform has a period of 3.333us or ~3333ns, if you sample this at say 100MHz (10ns period), then you will have errors due to synchronizer delays, and so can probably only measure the relative phase to around 30ns accuracy, which is 30/3333*100 = 1-percent error, which may not be bad.  The alternative is to use DSP and cross-correlate the signals, or use something like the Goertzel algorithm to extract the fundamental frequency for each signal and then cross-correlate the two signals to estimate the phase-difference.  Cheers, Dave

[Altera_Forum]

since it is 300KHz then you don't need much work. you can use simple counters or state machine but I have done a design before based on the following approach: 

 1) register both inputs twice on your clock  in1 => in1_1d => in1_2d  in2 => in2_1d => in2_2d  2) run two flips one clocked by in1 and one clocked by in2  if in1 edge arrives set flip1 output to '1'  if in2 edge arrives set flip2 output to '1';  and apply async reset if both these outputs are '1'; (this will be a short glitch but should do)  3) run two counters on your system clk  count1 enabled if flip1 output = '1  count2 enabled if flip2 output = '1'  asynchronously reset both counters if in1_2d = '1' and in2_2d = '1';  4) assign delay as signed value  if count1 > count2 then it is +count1  else it is minus count2

[Altera_Forum]

Thanks much! I think that's all I need to get this done