Clock Generation Block of Cyclone10GX Native PHY.

[LTN]

Hi Intel,

When I try to use the Native PHY IP Core in Quartus Pro 19.1, I choose the 10GBASE-R reset. I read the user guide of this ip core,in "2.6.2 10GBASE-R and 10GBASE-R with IEEE 1588v2 Variants" it describes the Clock Generation Block like this:

Could you tell me where do the three Serial clocks come from? 

Then, I use the ATX PLL to generate a clock in 5156.25MHz, and link it to PHY, but CGB did not generate tx_clkout and rx_clkout as expected,do you know why?

Thanks,

Li.