Clock and frame sync on LVDS link, Cyclone 5

[Altera_Forum]

Hi all, 

I am to design a connection between two cyclone 5 gx on our upcoming boards. There shall be 4-16 bidirectional links with speed 300-800mb each,  running on kind of backplane + boards assembly. I would like to avoid using transceivers due to its limited count and higher cost of FPGAs. Also, I would like to keep just minimal count of wires for each link (1 pair for Rx, one for Tx, no clocks, no frame sync) if possible.  So I am considering to implement simple "transceiver like" approach using lvds but with slower frequencies.   My raw idea: - Rx side with ALTLVDS_RX plus external PLL + 8/10 decoder in LEs - "some" logic to sync frames.. I could transmit special pattern or to use "start-stop" or other technique ? - Tx side with ALTLVDS_TX + 8/10 encoding and "some" training state logic - Mutual feedback about "locked" state  Since I am to design both side of communication, I am free to implement whatever approach is feasible. On the other hand I am quite a newbie, so this will be a big challenge in all cases :cool:  I would appreciate any opinions from you - experienced guys. Could you say if it is viable solution or to suggest other approach ?  Also any related resources/examples are welcome.  Thanks Alex