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Clock divider simulation problem

TAdel1
Beginner
439 Views

Hello there ,

I tried to code this clock divider to divide my input clock by 16 , but when I run simulation I got my output signal period same as my input clock , any one please can tell me why that happened ? my code

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_unsigned.all;

ENTITY TRICK IS

PORT ( CLK : IN STD_LOGIC;

    F : OUT STD_LOGIC);

END TRICK;

ARCHITECTURE BEH OF TRICK IS 

SIGNAL CNT : STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

PROCESS (CLK) IS

BEGIN 

 IF (CLK'EVENT AND CLK='1') THEN

  CNT<= CNT + 1;

  ELSE 

   CNT<=CNT;

  END IF;

F<=CNT(3);

END PROCESS;

END BEH;

0 Kudos
2 Replies
Vicky1
Employee
70 Views

Hi,

what you observed in simulation result? please provide screenshot.

Have you initialized the inputs(CLK) & outputs(F,CNT) in testbench?

 

Regards,

Vicky

Vicky1
Employee
70 Views

Hi,

May I know any update?

Should I consider that, case to be closed?

Regards,

Vicky

Reply