I'm using the MAX 10 10M08SAU169C8G in a new design. The documentation on the ADC (core only) is not clear. to me.
Would someone tell me what peripheral clock frequency is required when using a 10MHz pll-input freq. to produce a 1us running sample rate?
I am Farabi who will support you on this request. Please allow me sometime to get the details information on the ADC for MAX10.
I will get back to you once I have the information you requested asap.
The ADC on the 10M08SAU169C8G takes two clocks. The first clock is from the output of PLL1 c0 and it's set to 10MHz. The second clock is the peripheral clock. I still don't know what frequency I need to feed to the ADC's peripheral clock.
I tried using 10MHz as the peripheral clock,. 10MHz didn't work as the peripheral clock. I also tried 1MHz which didn't work either. Then I tried to discover which frequency will work. I found that 3 to 7MHz worked but I don't feel comfortable using these odd frequencies.
My request is; What peripheral clock frequency is needed when using 10MHz as the adc_pll_clock input?
The peripheral clock only used when you cant occupy PLL clk that connected to feed ADC clock. By default, MAX10 will use dedicated clock which is coming from the PLL, and the default frequency is 10Mhz.
If you want 1us interval sampling data, 10Mhz dedicated clock from PLL to ADC clock is sufficient.
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