Compensating for phase difference between transceiver outputs
I'm encountering an issue concerning phase differences between transceiver output channels. Here's a description of my problem. I need to transmit eight data streams/waveforms that are generated on a Stratix IV EP4SGX230KF40C2 FPGA. The logic seems to work and the transceivers appear to be properly configured (Protocol: Basic, Subprotocol: x4, Number of Channels: 4, Block Width: 40, Base Setting: Data Rate, Effective Data Rate: 6250.0 Mbps, Input Clock Frequency: 312.5 MHz). The problem I'm encountering is that there is a noticeable phase difference between the transceiver channel outputs. To explain, one transceiver block is associated with channels 1-4 (block one), and another transceiver block is associated with channels 5-8 (block two). If I transmit the same waveform on channels 1-4, I can confirm that they are all in phase. The same is true with channels 5-8; they are in phase. But relative to one another, channels 1-4 compared to channels 5-8, there is a noticeable phase difference. Now I'm aware that transceiver blocks on the same side of the FPGA (right or left) can be bonded together. Specifically, I could put them in x8 bonded mode and they will be driven by the same clock network. However, I'm stuck using the Terasic TR4 development kit (http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=138&no=683) and its associated XTS-HSMC daughter cards. Unfortunately, the transceivers that I have access to are on opposite sides of the FPGA so I can't use bonded mode. That said, is there anyway to synchronize the clocks of transceiver cores that happen to be on opposite sides of the FPGA? Any help is appreciated.