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New Contributor I
254 Views

Complex FPGA verification methodology

Dear members,

I have a complex FPGA design mostly built from schematic entry method( > 100 schematics) and a few VHDL files. I am new to verification topics and hence wanted to know what is the best method to verify the complete FPGA design. My questions are:

 

1) Will writing only the testbench for the top level design help, or should I verify each and every schematic individually by writing testbench to each of them.

2) Should I use System verilog(or other languages) for writing testbench, or writing them in VHDL is fine? I have experience of writing testbenches only in VHDL.

3) Kindly provide link to any resource or guides which could help me in this verification task in Quartus Prime.

 

Thank you very much in advance!

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2 Replies
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Employee
35 Views

Hi,

Welcome to Intel community!

Generally VHDL, Verilog, System Verilog languages are used for verification but for verification of huge & complex designs verification methodologies are recommended, for example OVM, UVM etc.

To use these methodologies, user must have knowledge of all languages, methodologies & simulation tools. Since you are newbie in verification & familiar only with VHDL, I would like to suggest with Quartus tool,

1) Will writing only the testbench for the top level design help, or should I verify each and every schematic individually by writing testbench to each of them.

-> If you are using pre-verified schematics then you can directly write test bench for top level design else need to verify each & every module. you can use waveform editor : https://www.youtube.com/watch?v=a8JAkKhxlQI

2) Should I use System verilog(or other languages) for writing testbench, or writing them in VHDL is fine? I have experience of writing testbenches only in VHDL.

-> Since you are experience with VHDL, make use of VHDL or waveform editor. If you want explore the verilog, system verilog please go through the 'Fundamental Par 1 & 2' online free Intel training : https://www.intel.com/content/www/us/en/programmable/support/training/catalog.html

3) Kindly provide link to any resource or guides which could help me in this verification task in Quartus Prime.

-> you can use waveform editor, simulation using Native Link & just go through the Intel online training : https://www.youtube.com/watch?v=PmVVXQchv2c

 

Regards,

Vicky

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New Contributor I
35 Views

Hello Vicky,

 

Thank you for your answer. I will go through the links provided.

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