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Altera_Forum
Honored Contributor I
2,218 Views

Component is outside master's address range

Hi, 

I have 2 Avalon MM Master components and 1 Avalon MM Slave. If I connect them together - to one slave I get error: 

Error: System.stream2eth.avalon_master: DM9000A.s1 (0x11048..0x1104b) is outside the master's address range (0x0..0x1)  

Address of the slave is 1 bit wide, same as addresses from both masters. I have tried "System -> Assign base adresses" but nothing. Screenshot from Qsys is attached. 

Does anybody know what is the problem?
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8 Replies
Altera_Forum
Honored Contributor I
459 Views

I forgot, that one master is default Nios processor. So the address from Nios can be 32 bit wide... but component DM9000A_IF has only 1 bit wide address.

Altera_Forum
Honored Contributor I
459 Views

Same problem i have please anybody give replies..

Altera_Forum
Honored Contributor I
459 Views

First the slave seems to cover a 4 byte space, so the master would need at least a 2-bit address to cover it (from the master side the address is always a byte address). Second, your slave is currently mapped at the address 0x11048, so the master would need at least 17 bits on its address vector to properly address the slave. 

You need a wider address bus on your master. I always use 32-bit address buses on my masters to avoid those kind of problems.
Altera_Forum
Honored Contributor I
459 Views

I have a MP32 cpu with an on-chip memory. Each time I add the cpu there is no error. But once I close the SOPC Builder and open it again, I get the same error: 

 

error: cpu.instruction_master: onchip_memory2.s1 (0x40000..0x7ffff) is outside the master's address range (0x0..0x1) 

 

I have already tried assign base addresses, but no change! 

Can anybody help?  

 

Thanks in advance
Altera_Forum
Honored Contributor I
459 Views

There seems to be something wrong with the CPU's instruction master, as it seems that SOPC Builder believes its address bus is only 1 bit wide. I've never used that core, but is there any setting related to the instruction master? Something about instruction address space size, maybe?

Altera_Forum
Honored Contributor I
459 Views

Thanks for your prompt help! 

There is something in cpu's edit page. I put the screenshot bellow. 

Shall I look for it somewhere else?
Altera_Forum
Honored Contributor I
459 Views

If there is anything it should be in that window. 

Unfortunately I don't know this core so it's hard to figure out what's wrong. Since you have an instruction cache that's already bigger than the master address space it looks like a bug. Maybe you should ask SLS for support.
Altera_Forum
Honored Contributor I
459 Views

Hello Everyone, 

 

In order to get the solution of this type errors,Master port must have 32-bit width,and use byte enable signal for how many byes you want to use. Previously i got the same error,after that i got the solution from the same forum. 

 

-Vasireddyrajesh3.
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