Config pins as normal IO pins

[CLa_R]

I would like to use JTAGEN, DEV_CLRn, DEV_OE and CONFIG_SEL pins, as normal IO pins, is it possible? To be able to do it do I have to create an external circuit or is only a quartus II configuration sufficient?

For the JTAGEN pin I connected a 1KOhm resistor between the pin and the ground, is it correct in this case?

Also, is it possible to use JTAG configuration pins (TMS,TCK,TD0,TD1) for the same purpose? How?

[ak6dn]

What device?

[CLa_R]

Max10 (10M08SCE and 10M40SCE)

[ak6dn]

Ok, so have you read:  "Intel® MAX® 10 FPGA Configuration User Guide" (ug_m10_config.pdf) Chapter 3? Talks all about how to do this.

[CLa_R]

Yes, I read it, but for me is a bit unclear.

Example: in "Table 3-1: Dual-Purpose Configuration Pin Guidelines for MAX 10 Devices" I read:

(for nConfig, nStatus, CONF_DONE) "During initialization:
• tri-state the external I/O driver and drive an external pull-up resistor(6) or
• use the external I/O driver to drive the pins to the state same as the external weak pullup resistor"

Whath exactly means?

I can't exactly distinguish user mode from initialization mode.

Aren't there any example circuits that show you how?

[ak6dn]

The 'normal' use of those pins is to have 10K pullups on them to VCCIO for their bank.

Figure 10 in section 2.3.1 shows the flow on how pins nCONFIG, nSTATUS, CONF_DONE are used during initialization.

You can't change that, this is BEFORE your internal POF image is programmed into the device.

Other I/O pins are all tristated.

When CONF_DONE transitions from being internally driven low to be pulled high, then the device is done being initialized.

Until this time, you CANNOT drive signals onto those three configuration lines, and you have to accept their levels.

Personally, I think it is VERY BAD practice to use those three lines as user programmable I/O. You will regret it.

Same for the four JTAG lines. Save them for jTAG access programming / debug. You won't regret it.

If you really need 7 more I/Os, use a bigger device, or figure out how to multiplex some of the regular I/Os to expand capability.

Just my 2c.

[CLa_R]

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When CONF_DONE transitions from being internally driven low to be pulled high, then the device is done being initialized.

Until this time, you CANNOT drive signals onto those three configuration lines, and you have to accept their levels.

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Ok, this shouldn't be a problem, I wouldn't use those pins before device initialization. (But I don't think anything can be done before or during initialization) 

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Personally, I think it is VERY BAD practice to use those three lines as user programmable I/O. You will regret it.

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Okay, but if they say it's possible to do it, why should that be a bad idea? I'm afraid that no one has ever actually tried it.

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If you really need 7 more I/Os, use a bigger device,

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I thought about it, but I should switch to a 256pins device, with increased complexity even in the PCB.

If it is possible to do this with the current device, why not do it?

As I wrote before, I'm afraid that what you read in the documentation has never been tried by anyone or is it really a bad idea to do it, as you told me. For this I am looking for concrete solutions that have already been tested, I do not trust the documentation (however rigorous it may be), but I would like some example circuits that have already been tested.

[ak6dn · Accepted solution]

Well, for reference I have about two dozen Altera FPGA production designs I have done over that last two decades, and never have I reused the configuration/status pins as normal I/O, or the JTAG pins either. They are all dedicated to their specific functions. If I needed more I/O, I went to either a larger package with more I/O capability, or found some way to multiplex existing I/Os (like using an external 8bit shift register device as an I/O expander, for example). Again just my 2c.

[CLa_R]

This is very convincing!