Configuration Failure | nSTATUS low, JTAG Chain Alive, AS Active Serial

[Altera_Forum]

I have ran into a configuration issue for my Cyclone IV. On one board I am able to configure, on a second board my FPGA is stuck at "reset." The FPGA is set for AS configuration but since nSTATUS never releases, the FPGA never retreives configuration data from the EPCS4 memory (DCLK never shows activity).  

 Interestingly, JTAG is alive. I can ID the device but upon programming via JTAG, CONF_DONE never releases and the FPGA remains at "reset." The Quartus Software looses the device and I need to rescan to pick it up. It does report a success for programming though. With a 3rd party tool, I am able to access the JTAG chain and perform a boundary scan. It passes ident, capture and an interconnect test. I also can toggle LEDs connected to the FPGA with a boundary scan test.  The device appears to make it through POR but gets stuck at reset. Any suggestions?  The pins are relatively static and don't display any activity. nCONFIG can be manually pulled high/low through a jumper.  OBSERVATIONS -nCONFIG | High/Low (Jumper). When Jumper removed 10k Pull Up. -nSTATUS | Low. 10k Pull Up. -CONF_DONE | Low. 10k Pull Up. -nCS | Low. 10k Pull Down -MSEL1 | 3.3V. Tied directly to 3.3V. -MSEL0 | 0V. Tied directly to GND. -Power Rails Look Good (VCCINT/VCCA_PLL/VCCD_PLL/VCCIO) -Ramp on rails looks good (Attempted to hold nCONFIG low when I apply power but didn't make a difference).  Reference Material http://www.altera.com/literature/hb/cfg/cfg_cf51001.pdf Reference Posts (Similar Issues but JTAG was dead) http://www.alteraforum.com/forum/showthread.php?t=5854&page=2 http://www.alteraforum.com/forum/archive/index.php/t-28545.html http://www.alteraforum.com/forum/archive/index.php/t-31638.html

[Altera_Forum]

An X-Ray of the pads of the FPGA failed to reveal any shorts. This left me rechecking the power rails for proper voltage and configuration pins to ensure they were properly handled. 

 The next action that was taken was to replace the FPGA. Surprise, surprise, the FPGA immediately configured using “Active Serial Mode” and the image from the EEPROM I had already programmed before I sent the board out. Either a solder short that was not seen by the x-ray was holding it in reset or the FPGA was damaged. Now I am curious if I could have just reflowed the FPGA and if a solder short was the actual problem rather then replacing the entire FPGA (after all JTAG was operational to perform a boundary scan, JTAG configruation would fail before the replacement).

[Altera_Forum]

--- Quote Start ---  I have ran into a configuration issue for my Cyclone IV. On one board I am able to configure, on a second board my FPGA is stuck at "reset." The FPGA is set for AS configuration but since nSTATUS never releases, the FPGA never retreives configuration data from the EPCS4 memory (DCLK never shows activity).   Interestingly, JTAG is alive. I can ID the device but upon programming via JTAG, CONF_DONE never releases and the FPGA remains at "reset." The Quartus Software looses the device and I need to rescan to pick it up. It does report a success for programming though. With a 3rd party tool, I am able to access the JTAG chain and perform a boundary scan. It passes ident, capture and an interconnect test. I also can toggle LEDs connected to the FPGA with a boundary scan test.  The device appears to make it through POR but gets stuck at reset. Any suggestions?  The pins are relatively static and don't display any activity. nCONFIG can be manually pulled high/low through a jumper.  OBSERVATIONS -nCONFIG | High/Low (Jumper). When Jumper removed 10k Pull Up. -nSTATUS | Low. 10k Pull Up. -CONF_DONE | Low. 10k Pull Up. -nCS | Low. 10k Pull Down -MSEL1 | 3.3V. Tied directly to 3.3V. -MSEL0 | 0V. Tied directly to GND. -Power Rails Look Good (VCCINT/VCCA_PLL/VCCD_PLL/VCCIO) -Ramp on rails looks good (Attempted to hold nCONFIG low when I apply power but didn't make a difference).  Reference Material http://www.altera.com/literature/hb/cfg/cfg_cf51001.pdf Reference Posts (Similar Issues but JTAG was dead) http://www.alteraforum.com/forum/showthread.php?t=5854&page=2 http://www.alteraforum.com/forum/archive/index.php/t-28545.html http://www.alteraforum.com/forum/archive/index.php/t-31638.html  --- Quote End ---      Hi,   We are having the similar issue with Arria V FPGA. Which is the Third party tool you had used for boundary scan? Could you please let us know.  Thanks & Regards, Nanjunda M