Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
19074 Discussions

Configuration and JTAG pin settings

NShan12
New Contributor I
201 Views

Hello,

 

I am using Cyclone 10 device 10CL040U484. How do I assign the EPCQ configuration pins as Input or Output? Are these automatically configured based on Quartus settings (Active serial configuration)?

 

NShan12_0-1623763096713.png

 

What should be the settings for Active serial configuration (using EPCQ16A, for ex) for the following pins?

NShan12_1-1623763326311.png

 

What about JTAG pins? Should I configure them in Pin planner?

Is there any setting where I should enable JTAG?

 

Thank you! Your answers and suggestions are highly appreciated.

0 Kudos
3 Replies
NurAiman_M_Intel
Employee
187 Views

Hi,


Thank you for contacting Intel community.


Kindly refer to Cyclone 10 LP pin connection guidelines and handbook.


Pin connection guideline: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-10/pcg-01021.pdf


Handbook: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10lp-51003.p...


Let me know if you need further assistance.


Regards,

Aiman


NShan12
New Contributor I
166 Views

Thank you! Reading it and proceeding with schematic design.

NurAiman_M_Intel
Employee
158 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Reply