Connection between 3.3V CMOS/TTL signal and 2.5V bank.

[AGofs]

Hi everyone,

I'm working with Cyclone V-GX .

Is it possible to connect 3.3V signal to FPGA pin (as an incoming port), which located on 2.5V bank (without any damage to this pin)?

it was possible at Cyclone III,as I knew,....

[ChiaLing_T_Intel]

​Hi AGofs,

Thank you for contacting Intel Community. According to Cyclone V device handbook, the Cyclone V architecture supports the Multivolt I/O interface feature that allows Cyclone V devices in all packages to interface with I/O systems that have different supply voltages. However, please be noted that the VCCIO of 2.5V can only have the output signal 2.5V. Please refer to the Table 5.10 for the allowable input signal of different VCCIO:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v2.pdf

To understand more in the Cyclone V multivolt application, you may refer to AN447 document for details.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an447.pdf

Furthermore, you may refer to the solution link below for understanding on how can devices support Multivolt input when the I/O specification limit Vih relative to VCCIO voltage.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd05102011_241.html

Thank you

Regards,

Chia Ling

[AGofs]

Good morning Chia Ling,

Thank you a lot for a quick and efficient answer!

I think you can close the case.

Thank you once again,

AGofs.