Constraining Derived External Clocks

[Altera_Forum]

I have an external reference clock coming into the fabric through the PLL (lets call it clk1 at the output of the PLL) 

I then divide this clock and send it out to the pins to an external (board) clock network to multiple devices including myself. Lastly I take the divided clock as an input through another set of pins into another PLL (lets call it clk2 at the output of the 2nd PLL) The PLLs are just used to maintain phase alignment to the reference clocks.  To simplify lets assume the division is by 2.  Can we tell timequest that the clk1 and clk2 are related? How can I model the skew and other board/device effects on clk2 so that timing path between clk1 and clk2 is captured accurately.  Gracias,   Cecil

[Altera_Forum]

--- Quote Start ---  I have an external reference clock coming into the fabric through the PLL (lets call it clk1 at the output of the PLL) I then divide this clock and send it out to the pins to an external (board) clock network to multiple devices including myself. Lastly I take the divided clock as an input through another set of pins into another PLL (lets call it clk2 at the output of the 2nd PLL) The PLLs are just used to maintain phase alignment to the reference clocks.  To simplify lets assume the division is by 2.  Can we tell timequest that the clk1 and clk2 are related? How can I model the skew and other board/device effects on clk2 so that timing path between clk1 and clk2 is captured accurately.  Gracias,   Cecil  --- Quote End ---    details of fedback clocks are given in the follwing document: https://www.mixdown.ca/redmine/attachments/download/71/timing_analysis_of_internally_generated_clocks_in_timequest_v2.0.pdf

[Altera_Forum]

Hi Kaz, thank you so much for kind reply. will this set_clock_latency take care of the routing delay from fabric to pad and back for the derived clock?

[Altera_Forum]

--- Quote Start ---  Hi Kaz, thank you so much for kind reply. will this set_clock_latency take care of the routing delay from fabric to pad and back for the derived clock?  --- Quote End ---    I notice you named your input clock as output of PLL. That is not what TimeQuest sees. your first clock input is that at pin (well before PLL) i.e. the reference clock. It is up to to the tool to work out any fpga internal delays from pin to PLL input to PLL output ...etc.  Then you send it out then in again. So you have three clocks at fpga to define (two input clocks and one output). Regarding set_clock_latency I assume it is about delays outside fpga pins.