Could a dual clock dual input DFF be implemented in FPGA?

[Altera_Forum]

Could a dual clock dual input DFF be implemented in FPGA?  

What I need is : process (clk1,clk2)  begin   if ( (clk1'event) and (clk1 ='1'))   then  dout<=din1;  end if;  if ( (clk2'event) and (clk2 ='1'))  then   dout<=din2;  end if; end process;   The minimum distance between the rising edge of clk1 and clk2 is more than 10ns.

[Altera_Forum]

Physically, there is no such thing as a two-edge register. Do you know the maximum distance between the rising edges of clk1 and clk2? Are the duty cycles 50/50? You might be able to build a mux that chooses which clock drives the register(this is a tricky thing to do, so don't tread lightly), but would require a known relationship between the clocks. 

Or, maybe have two registers grabbing the data separately, and then muxing between their outputs?

[Altera_Forum]

The maximum distance between the rising edges of clk1 and clk2 is 1us. 

Yes,both clk1 and clk2 is 50% duty cycle.  In fact ,clk1 and clk2 is the output of the same pll, with the same frequncy and differrent phases. The phase distance could be progammed.( range 10ns to 1us).

[Altera_Forum]

Actually, I think the problem is too isolated. What are you doing after capturing the data? You can't use both clk1 and clk2 simultaneously throughout your design(there is no such thing as a dual-edge register), so you're going to have to settle on clk1, clk2, or a third clock not yet described. If you settle on clk1, then it's only going to be able to take in half the data. Same as clk2. The other option is to keep the data as two parallel lanes, i.e. d1 and d2. If that's the case, you can then synchronize them both back to your system clock domain(clk1, clk2 or other) and use them that way.

[Altera_Forum]

If there is no overlapping of the clocks and they are of the same freq, this is nothing than a set-reset behaviour. You can setup a toggle FF for each of the clocks and add the output. Thus the ouput becomes odd after the first clock and even after the second clock rise. Bit 0 of this adder is the selector for the MUX