Could the refclk_1 of Cyclone IV GX (EP4CGX50CF23I7) be input refclk of transceiver?

[Altera_Forum]

Hi, all: 

  I'm using Cyclone IV GX (EP4CGX50CF23I7) to design some SerDes project. When I assign the refclk_1 pin (BANK 3B, REFCLK_1 , M8、N8) to the pll_clkin of transceiver, it can't Place & Route in Quartus II, the err message as below:  Error (176559): Can't place MPLL or GPLL PLL "serdes_icore:u_serdes_icore|serdes_icore_alt_c3gxb:serdes_icore_alt_c3gxb_component|altpll:pll0|altpll_4f81:auto_generated|pll1" in PLL location PLL_5 because I/O cell "tx_ref_clk" cannot be placed in I/O pin Pin_M8 (port type INCLK of the PLL)   When I change the pin assignment with refclk_2 (BANK 3A, REFCLK_1, M11,N11), and the compilation was successful.    So, here is my question——Could the refclk_1 of Cyclone IV GX (EP4CGX50CF23I7) be input refclk of transceiver? I looked up the related datasheet, and find no statements said it can't be. Was some settings I missed in Quartus II , due to this problem?  Thanks in advance.

[Altera_Forum]

There are restrictions regarding which clock pins connect to which PLLs. Refer to Figure 5-9 on page 5-20 of the "cyclone iv device handbook (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-iv/cyiv-5v1.pdf)". See note (1) 

  --- Quote Start ---  Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.  --- Quote End ---    Refer to the specific device pinouts for the location of these clock pins.  Cheers, Alex

[Altera_Forum]

--- Quote Start ---  There are restrictions regarding which clock pins connect to which PLLs. Refer to Figure 5-9 on page 5-20 of the "cyclone iv device handbook (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-iv/cyiv-5v1.pdf)". See note (1)   Refer to the specific device pinouts for the location of these clock pins.  Cheers, Alex  --- Quote End ---     Thanks for your answer. But Figure 5-9 is PLL internal block diagram, and it refers that the clock source can come from any of the four clock pins located on the same side as the PLL.  According to Figure 5-3 of the same handbook, refclk_1 should be used as input clock of PLL_5. But when I placed the pin as input clock, the compilation was unsuccessful. https://alteraforum.com/forum/attachment.php?attachmentid=13449&stc=1

[Altera_Forum]

Agreed. On the face of it you should be able to feed that PLL from that clock pin. So, I suggest you have another conflicting constraint that's causing the problem. 

 Can you realise a fit by removing all other constraints and leaving only the clock pin assignment?  Cheers, Alex

[Altera_Forum]

I had already tried that before I post this question.

[Altera_Forum]

--- Quote Start ---  Agreed. On the face of it you should be able to feed that PLL from that clock pin. So, I suggest you have another conflicting constraint that's causing the problem.  Can you realise a fit by removing all other constraints and leaving only the clock pin assignment?  Cheers, Alex  --- Quote End ---    I had already tried that before I post this question.

[Altera_Forum]

--- Quote Start ---  I had already tried that before I post this question.  --- Quote End ---    hello, I have encountered the same problem. The board design only have REFCLK1 and REFCLK4. But it seems that I can only use REFCLK2 and REFCLK3 in cyclone iv GX device. So I am very curious have you ever solved this problem???