Hello all, I'm new to this Altera world. Nice to have this forum that we can share something. I would like to make a pluse generate after every 8 clock signal. But the result is different, later pluse is always less than expect.Here is the code: always@ (posedge sclk or posedge cs) begin if(cs) begin counter<=0; flag<=0; end else if(counter<8) begin counter <= counter +1; flag<=0; end else// begin counter <=0; flag<=1; end// end It's funnny that if I remove the part within //..//, and use flip flop instead of pluse, the result seems correct. Could anybody help on this? Thanks.
What's the size of reg counter? If it's 3 bit, the else section will be never reached. If it's 4 bit or more, the counter will divide by 9 rather than 8.
@FvM, thank a lot for your fast response!My counter is "reg [7:0]", so it is 8 bits wide. I'm not sure that you said the counter should divide by 9 not 8 is correct. I have tried 7,8,9, seams not OK. The result when I use 8 is, the flag show at first 8th clock positive edge, but the second flag show at next 7th(15th from the beginning) clock positive edge. The test totally generate 16 clock in real CPLD device MAX II E240. The ModelSim result with test bench show correct flag wave, which is different to real one.:confused: