Create a on-chip memory with logic resources

[Altera_Forum]

Is it possible to create on-chip memory with logic resources in Altera FPGA when there's no enough on-chip RAM? 

For example, using VHDL language:  type memory_type is array (0 to 15) of std_logic_vector(31 downto 0);  signal memory:memory_type; If I create a very large memory with logic resources, will it have a huge influence on the process of synthesis and fitter? That means, will it slow the process? Thanks.

[Altera_Forum]

Yes, there is an assignment you can add in the Assignment Editor that allows you to choose how to implement the memory. I forget the name of the assignment right now. 

 I don't know what the affect on compilation will be, but the memory itself will be lower performance than if you use a dedicated memory block.

[Altera_Forum]

I create two 128K×32 on-chip memory with logic resource in Arria 10 SoC，but the process of "Analysis and Elaboration" takes too long time and eventually failed because "out of memory in  

module quartus_map.exe". And my computer contains 32GB DDR3. Is there any solution for this problem? Thanks.

[Altera_Forum]

Try with a smaller memory first. It's possible this configuration uses too many logic elements in the FPGA

[Altera_Forum]

On chip memory uses huge amounts of logic resources, and takes a long time to synthesise. You may also struggle with timing. 

128k x32 using on chip memory is very large,and probably uses all (or more) of the chip resources. Logic should only really be used for very small rams. MLABs (memories from logic) are only 640 bit, (32x16 for example). the largest Stratix 10 has 47700 of these, so you get 763kx32 max.  If your code doesnt match the behaviour pattern for an MLAB or M20k, it will be built using registers, where memory capacity will be far smaller.