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MHEDA
Beginner
395 Views

Critical Warning 16248 (pin is placed too close with ADC pins) and TSD use.

Hi,

 

 

 

For my current project i use an IntelFPGA MAX10 (10M40DAF484) and i use a lot of the available IO's.

 

Moreover, i need to use the internal temperature sensor. So i add the hard ADC IP and my own control module. 

But when i run the PnR, i have critical warnings regarding to GPIO i used.

 

I can understand why the tool reports these warning, but as in only use TSD and no ADC dedicated inputs, is there a realy issue ? If not, is it possible to avoid those warnings ? If yes, well, i'll have a bigger problem (not enough IO).

 

Thanks for your help.

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7 Replies
AnandRaj_S_Intel
Employee
95 Views

Hi ,

 

Kindly find the below KDB for your reference. Maybe there is a chance of generation of noise by the GPIO pin, So better to follow the Quartus recommendation.

 

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/soluti...

 

Similar case

https://forums.intel.com/s/question/0D50P000042PPLJSA4/critical-warning-16248-pin-is-placed-too-clos...

 

Regards,

Anand

 

MHEDA
Beginner
95 Views

Hi,

 

i've read both link you've mentionned.

However in both cases, analog inputs are used with the ADC. In my case i only want to use the TSD, so no analog pins are used. Is the temperature sensor is impacted by the GPIO close to ADC pins ?

AnandRaj_S_Intel
Employee
95 Views

Hi,

 

It should not be an issue if you are not using analog pins of ADC and using appropriate banks for IO.

 

  1. Can you share information on the part number & IO banks used?

 

Regards

Anand

MHEDA
Beginner
95 Views

Hi

 

FPGA: MAX10, 10M40DAF484-I7G

 

IO Bank i used: 1B, 2, 3, 4, 5, 6, 7 and 8 (all except 1A)

 

And, i confirm that i don't use analog inputs (and it is not planified).

 

 

AnandRaj_S_Intel
Employee
95 Views

Hi,

 

Is the temperature sensor is impacted by the GPIO close to ADC pins ?

Yes, ADC Sampling is influenced by analong input and refrence voltages.

TSD data need to be sampled by with refrence voltage.

 

Try to avoid IO bank 1A , 1B & 8.

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 

Regards

Anand

MHEDA
Beginner
95 Views

I don't understand your answer.

 

You said that ADC Sampling is influenced by analog inputs. I agree, i read this point too in the IntelFPGA documentation. But TSD doesn't use input how it can be influenced by GPIO?

 

"TSD data need to be sampled by with refrence voltage" -> does it means by using an external reference voltage ? Or using internal reference is enough ?

 

Moreover i checked my pinout, and i use too many pins on those banks (1B and 8) to move them to the other banks.

 

AnandRaj_S_Intel
Employee
95 Views

okay,

 

TSD data need to be sampled by with reference voltage, We can use both internal/external reference voltage.

 

For your requirements, you can use Internal VREF & you can safely ignore the Critical Warning.

If we are not using ADC pin.

 

Regards

Anand

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