Cyclone 10 ESD problem

[Testman80]

Hi Guys
Im experiencing some issue with cyclone 10 hang upon esd zap.
Im implenting cyclone 10 in my product design. Upon applying esd to any expose pin in my product hangs the cyclone 10 and it require power cycle to recover it. No esd applied directly to fpga. I noticed the fpga 1.2V core voltage current drop upon esd zap.

[ChiaLing_T_Intel]

Hi Kumar,

Thank you for contacting Intel Community. I would like to further clarify below so that we can understand your questions clearly:

-       Are you seeing the Cyclone 10 hangs or reset when you applied ESD zap?

-       Did you observe any functional failure without ESD zap?

-       Is the 1.2V core voltage dropped when ESD zap applied?

As further confirmed with the internal team, the Cyclone 10 devices meet our ESD testing for CDM and HBM, at +/- 500V and +/- 2000V respectively. 

Thank you

Regards,

Chia Ling

[Testman80]

Hi Chia Ling
Im not zaping esd directly on fpga. The zaping points are on connectors which has zeners to protect. I dont see any permenant damage on fpga upon esd.
Im observing the config done pin goes low after zap together with 1.2v core current drop. It looks like fpga is out of configuration at this point.

[ChiaLing_T_Intel]

Hi Kumar,

As further confirm with the internal team, the ESD zap gun was not part of ESD qualification requirements, so we don’t have data/results available.

Intel Cyclone 10 LP devices contain POR circuitry to keep the device in a reset state until the power supply voltage levels have stabilized during power-up. If the voltage drop below the POR monitored level, the device will lose the configuration that will cause the config done to go low.

Thank you

Regards,

Chia Ling

[ChiaLing_T_Intel]

Hi Kumar,

Our experts will contact you on another platform for going through the issue together.

Thank you

Regards,

Chia Ling