Cyclone 10 GX (10CX085F672) Device Clock input

[sidsinha89]

Hello All,

I am starting to work with Intel FPGAs. I am currently preparing specifications for the new FPGA project. A part of it is to define pin assignment for the module.

In my design, I wish to have ~8 clock inputs. all these inputs are single-ended. I see in pin-out file that certain IOs are marked as Clk_2A_1p, Clk_2A_1n. I intend to use clk_2A_1p as my clock input to an internal ALTCLKCTRL block. Under this setup am I allowed to use the complimentary pin clk_2A_1n as IO or do I have to essentially leave it unconnected.

Also, same question goes for PLL_2A_CLK_OUT1p, PLL_2A_CLK_OUT1n. I intend to provide single-ended GTX clock to the respective PHY via PLL_2A_CLKOUT1p and to use PLL_2A_CLKOUT1n as IO

Thanks in advance!

[Ash_R_Intel]

Hi,

It depends upon the I/O standard assigned to the pin. Bank 2A is a LVDS I/O bank, which supports single-ended I/O standards upto 1.8V.

Refer Intel Cyclone 10 GX Core Fabric and General Purpose I/Os Handbook. 

Section 5.4.3, I/O Banks Groups in Intel Cyclone 10 GX Devices,

https://www.intel.com/content/www/us/en/programmable/documentation/vua1487061384661.html#rfl1487755214207

and

section 5.1.1, I/O and Differential I/O Buffers in Intel Cyclone 10 GX Devices, https://www.intel.com/content/www/us/en/programmable/documentation/vua1487061384661.html#sam1403481935742

Also refer the device pin-out table for more pin information.

Regards.

[sidsinha89]

Hello!

Thanks for the reply. I shall apologize for not clearly mentioning the relevant details.

All I/Os on FPGA are LVCMOS standard. No Differential I/Os. All banks (2J, 2K, 2L, 2A, 3A) shall be on 1.8V VCCIO.

Under these circumstances, am I right to conclude that I shall be able to use complimentary pins, for instance clk_2a_1n, as normal LVCMOS I/O while clk_2a_1p is used as clock input and connected to ALKCLKCTRL IP block?

[Ash_R_Intel]

HI,

Yes, you can use the n pin independently as a normal IO.

Regards.