I have a new project based on C10 GX and I am debugging the IO problem.
The device is 10GX220YF672, the IO bank 2L was design to interface 3V IO.
I download a counter design to verify the operation, it will toggle every 200 ms.
From waveform, the high level is only 0.9V instead of 3V that I am expected.
What would be the problem?
If my external devices boot earlier than FPGA, will it cause this issue?
Hi Johnson Lee,
Just want to check, have you set the IO Standard of Bank 2L to 3.0V?
It is not a problem for an external devices that boot earlier than FPGA if you obey the pin state as shown in the user guide:
For example, LVDS I/O banks need to be tristated (Setting in Quartus) while power up and vice versa.
Thank you for reply.
Yes, I did set the IO standard to 3.0V.
Attached is the qar file for your reference.
I test 2 boards with this configuration.
Both show the same status,
before config, gpio_0 is 3V, led_0 is 0.7V. After config, gpio_0 switch between 3V/ 0 V. led_0 is 0.9V/ 0V.
I just found the clock was not operated properly, amplitude is small..
I will check it and see if this is the root cause!
I have a question on the reference file.
From the table below, it means the external IO pin should be in Tristate during FPGA boot up ?
If above rule can’t be followed, what will happen to the device?
And what should I do to prevent this?
Boot external devices later than FPGA ?
Hi Johnson Lee,
No tri-stated is needed from external pin. During FPGA power up, the pin itself will tri-state for used pin. Meanwhile for unused pin, you will need to do some setting in Quartus to enable tri-stating.
To do so, go to "Assignments" -> "Device" -> "Device and pin info" -> "Unused pin" -> "As input tri-stated with weak pull up"