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Hi,
I was wondering why the Cyclone 10 GX dev kit schematic shows a separate set of decoupling capacitor for each bank even though some banks share the same rail. I'm working on a design with 3 close banks (A, J, K) sharing a +1.8V rail and have calculated everything using the PDN tool. Am I suppose to calculate the # of capacitors for each bank separately like what the dev kit has done, even though they share the same rail?
Thanks,
Michael
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Hi ,
If my above reply got confused really sorry about that , I am recommending to follow the PDN and to your question on 35 Capacitor , I assume you can connect to power rail.
For accurate results , I also recommend you to do simulation.
Kindly note the above is only recommendation,/suggestion .
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Hi ,
I will let you know all the Ztarget calculation is depends up on the power rails. And in the PDN, the report is shown as per the power rails.
But the power rail connection to the bank is also depends up on the PCB, so my recommendation is to follow the dev kit schematics as a reference
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Thanks for the response! For my own knowledge, could you also clarify why the dev kit split the VCCIO capacitors into different banks rather than group them together like the PDN tool?
My current PDN results shows that I need 35 bottom layer decoupling capacitors for the +1.8V plane, do I need to somehow divide those 35 capacitors for each bank? Or should I simply place those 35 capacitors as close as possible to the VCCIO pins as a whole group?
Regards,
Michael
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Hi ,
If my above reply got confused really sorry about that , I am recommending to follow the PDN and to your question on 35 Capacitor , I assume you can connect to power rail.
For accurate results , I also recommend you to do simulation.
Kindly note the above is only recommendation,/suggestion .
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Hi ,
Kindly let me know if you need further assistance
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Thanks! I think this pretty much answered my question.
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