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After compiling a EMIF for Cyclone 10 GX, I noticed that it insists on using an external differential clock. Attempts at routing internal PLL output to pll_ref_clk input results in error. Does that mean I have to use an external LVDS oscillator, or loop a differential PLL output back to this?
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Hi,
--- Quote Start --- After compiling a EMIF for Cyclone 10 GX, I noticed that it insists on using an external differential clock --- Quote End --- • This is user configurable option in C10 EMIF IP under PLL refclk section. • Set in EMIF IP thenuse the IO standard that being set in EMIF IP. --- Quote Start --- Attempts at routing internal PLL output to pll_ref_clk input results in error --- Quote End --- • Yes, this is expected. C10 EMIF PLL refclk need to come externally from board. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)- Mark as New
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Hello,
is this also applicable for Arria 10devices?
I have found a source that states that in Quartus II 14.1 and earlier, this was also not possible for Arria 10 FPGA, but I have the same problem with Quartus 17.1.
Why is it not possible to generate the EMIF ref clk with a PLL? The *_readme.txt file says, that the ref clk is optional.
Best regards
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