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Cyclone 10 GX IBIS input models


I'm using the Cyclone 10 GX. I'm trying to simulate a 1.8 V LVCMOS FPGA input with a 50 Ohm termination. Does Intel provide this kind of model?


I made another post about it but closed it too soon:


That post mentioned the 50 Ohm termination in the ramp section of the IBIS model, but as far as I am aware, the ramp section of the IBIS models are used for outputs, not for inputs. So that model would be for an output with a 50 Ohm source-series termination.


What I am looking for is a model of a 1.8 V LVCMOS FPGA input with the 50 Ohm parallel termination.

Maybe that model doesn't exist? If not, what is the intended method to simulate that situation? Do you have to place the parallel termination on your own, and would that even be accurate?


I see in the Excel spreadsheet that describes the models that some of them do in fact have 50 Ohm parallel terminations, just none of the 1.8 V LVCMOS models.

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I checked this with the internal team regarding this issue.

And they confirmed that, unfortunately no, it wasn’t supported for Cyclone 10 GX. You will need to use voltage referenced IO standard instead.

Apologies for the inconveniance.



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