Cyclone 10 GX Max I/O Voltage level input and CLKUSR

[jpang10]

Hi,

I am currently using Bank 2A partially for DDR3L (1.35V), which also has CLKUSR pin in the same bank. I am also using transceivers for PCIe, and I realized very late (after layout is 99% finished) that a 100MHz oscillator is required for CLKUSR pin to use transceivers.

1. Can 1.35V VCCIO bank take 1.8V inputs? In the Intel Cyclone 10 GX Core Fabric and General Purpose I/Os Handbook page 92, note (7), it said inputs for most I/O standards are powered by Vccpt, which is 1.8V. I am unable to find a single ended 100MHz oscillator with 1.35V output, or if you have any other suggestions?
2. Is there a requirement for the duty cycle for the CLKUSR pin? The datasheet only states that it needs to be between 100MHz and 125MHz, and if I am able to use a 1.8V oscillator then the duty cycle won't be 50%.

Thank you so much for your help.

[ShafiqY_Intel]

Hi JPang10,

The 1.35V Vccio bank cannot take 1.8V Input. 

The I/O bank will has conflicting Vccio setting and Quartus will failed to compile.

Regards,

Matt