Cyclone 10 GX power consumption optimization

[Rinalds]

Hello,

First time posting here.

We have designed custom PCB with Cyclone 10 GX FPGA (10CX220YU484I5G).

It has:

1. DP IP, configured with 4 x 8.1gbps transceivers;

2. NIOS CPU running at 100MHz;

3. Almost all I/O are utilized, 60 pairs of them are LVDS.

Due to limited heatsink options we encountered thermal problems.

To reduce FPGA power consumption we tried:

1. turn on different compiler power optimization settings -> no effect;

2. Reduce NIOS CPU frequency -> no effect (don't know why);

3. Reduce transceiver link rate from 8.1 to 5.4 gbps -> 10% power savings.

Power consmption is measured with - https://www.cypress.com/documentation/development-kitsboards/cy4500-ez-pd-protocol-analyzer

What else can be done, to reduce power consumption?

Select smaller device? Design fits into 10CX105YU484I5G?

Any advice is appreciated,

Rinalds

[Ash_R_Intel]

Hi,

Here are some resources for understanding power management techniques.

Quartus Power Analysis and Optimization User guide: https://www.intel.com/content/www/us/en/programmable/documentation/osq1513989409475.html#aju1526092500763

Early Power Estimator: https://www.intel.com/content/www/us/en/programmable/documentation/jlc1485535013520.html

Regards