I am having problems with a Cyclone 10 LP running a Nios processor that is writing spurious data to its configuration device on power down.
I'm using a 16Mbit SPI configuration device and the EPCQ Controller 2 to control it.
The device is set to configure in AS mode and the dual use pins are set to Regular IO on configuration completion as we read/write to part of the configuration device for permanent storage.
I have seen on an oscilloscope that the Chip select and Data lines to the configuration device start toggling on power down for about 600µs. I've also seen that the clock signal remains active even after the device has configured.
I've performed a test where I set the dual use pins to Compiler Configured and this stops the DCLK when configuration is complete.
I've looked at a previous project using a Cyclone III and the EPCS Controller with the dual use pins set to Regular IO and have seen all of the configuration signals become and stay static after configuration has ended.
Does any one have any ideas what might be going on? Especially why is the clock signal remaining active after configuration?
May I know which configuration device you are using for Cyclone 10 LP? (i.e EPCQ16, MT25Q256 or etc2)
Are you using your custom board or Intel Cyclone 10 LP Evaluation kit?
I tested my Intel Cyclone 10 LP Evaluation kit with EPCQ controller II IP, I did not get any corrupted byte on my flash and DCLK stop once configuration completed.
Maybe you can try to use Intel FPGA Generic QUAD SPI Controller II IP instead of EPCQ controller II.
(the EPCQ or QSPI controller II are the same in term of how to execute it. EPCQ wrap over hard asmi ip while QSPI wrap over soft asmi ip).
I'm using a EPCQ16 type device and it is on our own designed PCB.
I'm using Quartus 18.1 if that helps.
I have found that if I set the Dual Use pins option to Compiler Configured the DCLK stops but if I set the same pins to regular IO then the DCLK continues after configuration.
I will try your suggestion about the Quad SPI Controller - thanks
Which Dual-purpose pins you set as Compiler Configured? (i.e DCLK pins or Data [7..2] pin or etc2)
When you set Dual Use pins option to Compiler Configured the DCLK stops, did the spurious data still written to configuration device on power down?
I had set all of the dual use pins to Compiler configured. Only when I did that did the DCLK stop after configuration.
I have found that the DCLK continuing toggling is dependent on whether the EPCQ controller II is included in the Qsys build.
If I remove it from a project the DCLK stops after configuration.
However we use the top sector of the configuration device for non-volatile storage of design parameters so I need to be able to read/write to it after configuration. For this I believe I need to set the dual use pins to regular IO?