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I also tried to compile the design in 19.1 standard version, and it shows 4 Total PLLs. You can refer to the attached screenshot.
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Hello,
In your screenshot, it stated as 4 PLLs. So you can use 4 PLLs in this device.
regards,
Farabi
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Hi Farabi,
Thank you!
But why the Quartus report on the right side is "2"?
BRs,
Johnson
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Hi Johnson,
We try to reproduce a working simple design which utilizes 4 PLL on 10CL016U256C8G using Quartus Prime Standard 22.1 version.
It is showing the correct number which is 4 for Total PLLs.
It may be a typo you have seen there. I will report it to the engineering. Can you mention the specific version of Quartus that you use?
Regards,
Aqid
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I also tried to compile the design in 19.1 standard version, and it shows 4 Total PLLs. You can refer to the attached screenshot.
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Hi Aqid,
Thank you for the share.
I found the root cause as I enable the Migration Devices to smaller chip in the project....
BRs,
Johnson
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Hi Johnson,
Thank you for pointing this out. It will be a good reference for the community.
Really appreciate it.
As your question has been addressed, I now transition this thread to community support. If you have a new question, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Regards,
Aqid
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