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19698 Discussions

Cyclone 10 LP : fallback bitstream

Steve-534B46
Beginner
260 Views

Hello,

I am new to the Cyclone 10 LP FPGA.
I am looking for a way to handle a fallback bitstream in case the application bitstream update fails due to a power loss or something.

I saw two documents that discuss this feature:

  • Remote System Update for Cyclone 10 LP
  • Cyclone 10 LP Remote System Upgrade Design Example User Guide

However, the process is not clear to me.

Is there a document that explains the whole process and all the considerations behind it?
Moreover, is it functional with all configuration modes (AS, PS...)?

Thanks in advance

Best regards,

Steve

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5 Replies
YuanLi_S_Intel
Employee
222 Views

Hi Steve,


I believe remote system update can fulfill your desire. It is meant for AS configuration only.


Remote system update is to reconfigure your FPGA with another bitstream stored inside the flash. If there is anything happen during the reconfiguration process, it will fall back to factory image.


Hope this helps.


Best regards,

Bruce


Steve-534B46
Beginner
198 Views

Hi Bruce,

Another question : is there a document that describes which memories to use and which connections to make?

Is ASx4 possible on Cyclone 10 LP? Or is only ASx1 possible?

Best regards,

Steve

YuanLi_S_Intel
Employee
180 Views

Hi Steve, Yes it is possible for both ASx1 and ASx4


Steve-534B46
Beginner
166 Views

Hi Bruce,

I was wondering if there is a document that attests to this information?
Indeed, the following document (https://www.intel.com/content/www/us/en/support/programmable/articles/000076544.html) does not mention the ASx4 mode for the Cyclone 10 LP family.

Thanks in advance for your help.

Best regards,

Steve

YuanLi_S_Intel
Employee
148 Views

Hi Steve, yes you are right. It supports ASx1 only. We do mention that in the handbook.

https://www.intel.com/content/www/us/en/docs/programmable/683879/current/configuration.html


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