I am new to the Cyclone 10 LP FPGA.
I am looking for a way to handle a fallback bitstream in case the application bitstream update fails due to a power loss or something.
I saw two documents that discuss this feature:
- Remote System Update for Cyclone 10 LP
- Cyclone 10 LP Remote System Upgrade Design Example User Guide
However, the process is not clear to me.
Is there a document that explains the whole process and all the considerations behind it?
Moreover, is it functional with all configuration modes (AS, PS...)?
Thanks in advance
I believe remote system update can fulfill your desire. It is meant for AS configuration only.
Remote system update is to reconfigure your FPGA with another bitstream stored inside the flash. If there is anything happen during the reconfiguration process, it will fall back to factory image.
Hope this helps.
Another question : is there a document that describes which memories to use and which connections to make?
Is ASx4 possible on Cyclone 10 LP? Or is only ASx1 possible?
I was wondering if there is a document that attests to this information?
Indeed, the following document (https://www.intel.com/content/www/us/en/support/programmable/articles/000076544.html) does not mention the ASx4 mode for the Cyclone 10 LP family.
Thanks in advance for your help.