Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
The Intel sign-in experience is changing in February to support enhanced security controls. If you sign in, click here for more information.
19682 Discussions

Cyclone 10 LP unused PLL clkout signals

PYtte
New Contributor I
206 Views

I am reading through the "Intel® Cyclone® 10 LP Device Family Pin Connection Guidelines" and for PLL[1..4]_CLKOUTp and PLL[1..4]_CLKOUTn it just says

"When not using these pins, connect them as defined in Intel Quartus Prime software."

Can someone elaborate on this? Do I define them somewhere? Or are they defined by synthesizer?

I am only talking about them when not used of course. My initial thought it so connect them to ground.

EDIT: I see the same text for all DIFFIO_ signals as well.

0 Kudos
4 Replies
SyafieqS
Moderator
178 Views

Hi Peter,


This seem IO related issue, I am checking this internally and will back with findings


SyafieqS
Moderator
126 Views

Hi Peter,


"When not using these pins, connect them as defined in Intel Quartus Prime software."


Can someone elaborate on this? Do I define them somewhere? Or are they defined by synthesizer?

- Yes, as mentioned the undefined pins will be defined automatically by Quartus when not in using. You can see the it in compilation report -- Fitter --> pin-out file. 



SyafieqS
Moderator
102 Views

Peter,


Let me know if there is any update or concern at your end.



SyafieqS
Moderator
78 Views

We do not receive any response from you to the previous answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


Reply