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Cyclone 10 power down sequencing

mmorrocchi
Beginner
‎09-16-2021 08:39 AM
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Hi, I read in the user manual that Cyclone10 has specific requirements on the power-down sequence. To comply with these requirements we need to use more PCB area than that available in our board. Could you please specify which are the consequences of not respecting the power down requirements?

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AminT_Intel
Employee
‎09-23-2021 08:17 PM
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Hello,

 

We do not validate anything out of specs. Thus, customers will bare the risk of FPGAs if they decided to do something out of requirements from our documents.

Thank you.

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AminT_Intel
Employee
‎09-28-2021 01:34 AM
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In response to AminT_Intel

 We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

In response to AminT_Intel
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