Cyclone 10GX FPGA device 10CX105YF672I5G - Parallel CFI Flash connection pinouts

[ADTL_belveera]

We are using the Cyclone 10GX FPGA device 10CX105YF672I5G along with Micron make DDR3L device  MT41K128M16JT-125 and  Spansion make 16-bit NIOS compatible CFI Flash device S29GL256P10TFI010 in our design. Help us to find the appropriate pinouts to interface the Cyclone 10GX FPGA device with 16-bit Data and Address lines of the CFI Flash device.

[YuanLi_S_Intel]

Connection is depending on the configuration scheme you choose. Since you are using CFI flash, the configuration scheme should be passive configuration scheme. You may refer to our pin connection guidelines for the connection:

https://www.intel.com/content/www/us/en/docs/programmable/683417/current/device-family-pin-connection-guidelines.html

[ADTL_belveera]

Hi,

Thanks for your reply.

I have already referred the pin connection guidelines, but couldn't find specific Address lines for the CFI flash. Are there any specific lines to be connected as Parallel Flash address in the Cyclone 10GX FPGA device 10CX105YF672I5G or not? If yes, please tell us the specific pin numbers. 

Thanks in advance.

[YuanLi_S_Intel]

For address pin, you need to connect it with a Host Controller (CPLD / MAX / Processor).

https://www.intel.cn/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf#page=193