Cyclone 10LP Post Configuration BSDL

[Yadima]

Hi,

Does anyone have experience of generating and using post-configuration bsdl for boundary scan testing the CYCLONE 10 LP 10CL120F780?

The boundary scan test works with the pre-configuration bsdl, however, there's no response on output pins when running with the post-configuration bsdl.

I'm using Quartus Prime 23.1 (Lite Edition) to compile the design. I then run a tcl file (CYCLONE 10 Post Configuration BSDL Generator (C10.tcl)) to generate the bsdl, as the Lite Edition does not support post configuration file generation. The generated bsdl is attached.

Any ideas?

[FvM]

Hi,
to be honest, I don't know if there's a thing like post-configuration BSDL. I'm frequently running boundary scans on configured FPGA with topjtag probe, after simply importing the standard BSDL file.

[NurAiman_M_Intel]

Hi,

You may refer below for BSDL

https://www.intel.com/content/www/us/en/support/programmable/support-resources/board-layout/bsdl.html

Regards,

Aiman

[FvM]

Hi,
I read a bit about post-configuration BSDL after confessing that I did even know that such a thing exists.

It seems that I never missed anything with standard BSDL files because my test tool (TopJTAG Probe) already does what can be done in this regard. If loaded on top of a running configuration, it keeps all IO settings, displays pin states in SAMPLE mode and gives me the option to override individual pins in EXTEST.

Regards
Frank  

[Yadima · Accepted solution]

Hi Frank,

Thanks for responding to my query.

I have managed to resolve the issue. There were certain I/Os that were meant to operate in output mode only, but were configured as bidirectional. Reconfiguring these I/Os as outputs resolved the issue.