Cyclone II Configuration

[Altera_Forum]

Hello, 

 We are designing a system using Cyclone II FPGA, to decide which FPGA configuration should be used, I was reading the document "Configuring Cyclone II Devices" (referred below )  http://www.altera.com/literature/hb/cyc2/cyc2_cii51013.pdf?gsa_pos=3&wt.oss_r=1&wt.oss="configuration"%20"cyclone%20ii"  But from this document I did not figure out the following:  1- What are the advantages and disadvantages for each of the three configuration schemes (AS, PS & JTAG). How can I decide which configuration to use? :confused:  2- Does the AS configuration scheme consumes FPGA resources?   Thanks in advance :)

[Altera_Forum]

Hi, 

the difference ist  JTAG and PS requires "someone" to load data into the FPGA, which can be a Microcontroller (e.g. for PS) or the USB Blaster (e.g. for JTAG). If your design "just has the FPGA", the way to go is most likely the AS scheme, the FPGA connected to the ALTERA configuration EEPROM. As for this mode the FPGA generates the Clock for the serial interface with the configuration EEPROM itself, this option its called A(ctive) S(erial)... Decision is easy  - FPGA shall configure on power ON without any additional controller => AS - FPGA shall be programmed by Microcontroller (save bucks for the config EEPROM) => PS - FPGA shall be programmed during development tests => JTAG   To be honest, I can not imagine of JTAG to be the option for in real world operating systems - but anyone can correct me on this..  For me having no other controller besides the FPGA, I use AS mode.  HTH,  Carlhermann

[Altera_Forum]

Upps missed:  

The AS "logic" is hardwired inside the FPGA, not being part of the programmable part. Thus using AS mode does not impact available resources...

[Altera_Forum]

--- Quote Start ---  To be honest, I can not imagine of JTAG to be the option for in real world operating systems - but anyone can correct me on this..  --- Quote End ---   I don't think that JTAG is used as the only configuration option once in production either, but you should still think about putting a JTAG connection on the board anyway. First it can be used for debugging (and even after production, you can always need to debug something at any time) and during board manufacturing the connector can be used for boundary scan. So put a JTAG connector, in combination with PS or AS as explained by Carlhermann.

[Altera_Forum]

--- Quote Start ---  Hi, the difference ist  JTAG and PS requires "someone" to load data into the FPGA, which can be a Microcontroller (e.g. for PS) or the USB Blaster (e.g. for JTAG). If your design "just has the FPGA", the way to go is most likely the AS scheme, the FPGA connected to the ALTERA configuration EEPROM. As for this mode the FPGA generates the Clock for the serial interface with the configuration EEPROM itself, this option its called A(ctive) S(erial)... Decision is easy  - FPGA shall configure on power ON without any additional controller => AS - FPGA shall be programmed by Microcontroller (save bucks for the config EEPROM) => PS - FPGA shall be programmed during development tests => JTAG   To be honest, I can not imagine of JTAG to be the option for in real world operating systems - but anyone can correct me on this..  For me having no other controller besides the FPGA, I use AS mode.  HTH,  Carlhermann  --- Quote End ---    Hello,  Thank you very much for this valuable info.  Regarding the JTAG, I found in the same document (in my post) that, beside using the JTAG in testing, it can be used also with a microprocessor to configure the FPGA. In this case, what is the main differences between this scheme and the PS one.  Kind Regards

[Altera_Forum]

Hello, 

 Thank you very much for your help.  We decided to use AS as a configuration scheme (beside the JTAG that will be used in the design process).  We would like to confirm that the USBBlaster cable is the only cable required in this situation.  Thanks in advance.

[Altera_Forum]

Yes you can configure the FPGA and program the EPCS device with a USB blaster.

[Altera_Forum]

--- Quote Start ---  Yes you can configure the FPGA and program the EPCS device with a USB blaster.  --- Quote End ---    Hello,  Thank you very much, but is the same cable can be used in the design phase for both, downloading the FPGA configuration file as well as downloading/debugging the developed code in NIOS II IDE for Eclipse.  Kind Regards

[Altera_Forum]

Yes. As long as you enable the JTAG debug module in the Nios CPU and have a JTAG UART in the SOPC system, you can use the USB blaster to download and debug your software.