Hi,I am going to implement a 512-point 16-bit FFT core in a Cyclone II FPGA device. The FFT core itself needs 22 M4K RAM blocks and there are 36 M4K blocks available. Meanwhile, I also need to cache 2048-point 16-bit raw data in the on-chip RAM as well as the results of the FFT core, which is composed of 16-bit real and 16-bit imag, and 4-bit exponent, in total 512 36-bit, roughly 5 M4K blocks. So, I need to reserve 8 M4K blocks for Raw data storage, 5 M4K blocks for FFT results. My question is, if I create two megafunctions, one for raw data, 2048 16-bits of memory, and one for FFT output, 512 36-bits of memory. Will these memory be reserved and only accessible by instantiating the corresponding megafunctions? If the FFT core calls for memory, will it automatically use the rest of M4K blocks, or it will use whatever available, in other words, there's potential risk to overwrite the memory used for raw data or FFT output storage? Thanks, -Roger
Thank you for the reply. Let me elaborate it a little clearer. The Altera FFT megafunction does not allow the user to customize how the on-chip RAM is used. In other words, I don't know which chunk of RAM will be used by the FFT core when it is being instantiated. I need to use the on-chip RAM to store some data for future computation. So, my worry is that the RAM used by FFT core may be overlapping with the memory I used to store the data. My data may be overwritten by the FFT core during the computation if this is the case. So, I would like to get some hints on how the FFT core allocate Memory and how we can avoid such Memory conflict in the design.--- Quote Start --- How and why do you "reserve" RAM? Isn't the RAM instantiated inside the FFT core? --- Quote End ---
--- Quote Start --- So, my worry is that the RAM used by FFT core may be overlapping with the memory I used to store the data. My data may be overwritten by the FFT core during the computation if this is the case. --- Quote End --- That won't ever happen. There's no way how internal memory can be shared between multiple design blocks, it's always instantiated exclusively. You are apparently imagining FPGA block RAM as a resource similar to processor RAM connected through a common bus. Each FPGA RAM block has it's own data and address lines that are individually connected to logic. If you actually want to time share memory in special situations (very unusual) you need to define explicit multiplexers. You can review the Compilation Report/Fitter/Resource Section/RAM Summary for the RAM usage in your design. The same information is also in the Project Navigator/Hierarchy display.