Cyclone III and C

[Altera_Forum]

Hello.  

 We are a group of students that are trying to develop a system for near real-time video digitalization and streaming over a network.   To do this we will utilize the Cyclone III FPGA and a A/D converter card from Bitec.  We are now in the design phase of our project and are having some difficulties about what to implement in VHDL and C.  My question is as follows:  What functionality does C code offers to the FPGA, can it be used to run independent portions of code or is it only meant as an addition to the VHDL code?  Any input would be much appreciated.

[Altera_Forum]

VHDL is a hardware description language for modelling systems and designing logic. 

 C is a software language for writing code running on a processor.  Of course you can get various tools which convert VHDL into software and C into hardware but at the end of the day they are never going to be as good as using the right language for the right job in the first place.  If you're putting a NIOS processor into your FPGA then use C to write the software running on that processor. Use VHDL for designing the logic in the FPGA. If you're not using NIOS and you're just using the FPGA as an FPGA then use VHDL.  Of course there are a hundred and one opinions on this and you may well ressurrect another battle in the language war here; but I would add that you're doing a college project and the point of that is to learn: so try and get some experience of both languages so that you can form your own independent opinion of when to use what language.  Good luck.

[Altera_Forum]

In our FPGA work we tend to use software(C for nios) when dealing with slow and/or algorithmically complex work. Any fast data processing is left to hardware(firmware). 

The unit comms, user interface, any external configurations and other once only or so slow things are certainly left to software colleague if he/she is kind enough, if not you can do whatever you can in firmware until you are exhausted then seek the help of your manager to throw some work on the software team.   It is always useful to remember that you are not alone with your HDL fun and that you got software support for any difficult nasty tasks provided it is a match to software speed even if this task is a corner somewhere in the middle of your design.

[Altera_Forum]

Thank you for your replys. 

 I have one additonal question. About this subject.   Is it adviced to program the UDP and RTP protocols in C?

[Altera_Forum]

That would depend on how you're implementing the protocols - if you're implementing them in hardware then use VHDL; if you're doing it in software running on a processor (e.g. NIOS) then C.

[Altera_Forum]

Do we have to install a RTOS on the FPGA?  

And when dealing with a latency demand on latency<100ms from source to destination is VHDL the best option for the UDP and RTS protocols?

[Altera_Forum]

You can install a RTOS on the NIOS processor if you want - whether you do is up to you. 

 The best language (C or VHDL) isn't determinable from a latency requirement. You need to do the design on this: take your requirements, work out what you're going to do in hardware and what you're going to do in software, which will be affect by speed and capacity of the FPGA device that you're using. Then write your hardware in VHDL and your software in C.

[Altera_Forum]

--- Quote Start ---  You can install a RTOS on the NIOS processor if you want - whether you do is up to you.  The best language (C or VHDL) isn't determinable from a latency requirement. You need to do the design on this: take your requirements, work out what you're going to do in hardware and what you're going to do in software, which will be affect by speed and capacity of the FPGA device that you're using. Then write your hardware in VHDL and your software in C.  --- Quote End ---     Not to steal this thread, but I wondered about something. ;) Is there no UDP/IP stack available to use in SoPC-builder, free of charge? And if there is no available, implementing this yourself in VHDL/Verilog is a pain in the **s compared to C/C++?

[Altera_Forum]

--- Quote Start ---  Not to steal this thread, but I wondered about something. ;) Is there no UDP/IP stack available to use in SoPC-builder, free of charge? And if there is no available, implementing this yourself in VHDL/Verilog is a pain in the **s compared to C/C++?  --- Quote End ---    Steal away - the more the merrier.  In answer to your question / point - probably. Of course if you can pinch a design that has already been done for you then it makes life a lot easier.  What I was trying to get across was that the general point: that you need to decide on your hardware / software split based on the system requirements. The choice of language then comes down to whether you're designing the hardware or the software bit of the system. Designing an algorithm isn't easier or harder in VHDL / verilog or C, but designing hardware in VHDL is a lot easier than C; designing software in C is a lot easier than VHDL.

[Altera_Forum]

Okey, thanks for your answer batfink :)

[Altera_Forum]

You must be into the design by now. Whatever process you are using is of interest to me. 

The first thing that I did in design was to create a block diagram so that I could visualize the data movement, then look for the places where time is critical or where the manipulation is complex. Given that it is desired to do as much in C as possible, the ability of the processor to meet the time requirements is the next point. One project I worked on was to define a set of adapters to attach various devices to a micro-controller. Management had been sold on the concept that any logic function could be programmed, which is true. However just because it CAN does NOT IMPLY that should. If and only if it meets timing, then it should.  If you generate any C code that you can share with me, I will appreciate it very much. My project is a new kind of embedded processor that is designed to execute C code very fast. In order to evaluate, I need more test cases.  Wishing you great success. Know you are up to here in busy, so thanks for your time! Karl  By the way, this design phase is the most important although I'm afraid there's not enough emphasis.