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Cyclone III slave (PS) embedded memory errors

Vic3Dexe
New Contributor I
756 Views

I have two Cyc III devices (master-slave, AS and PS respectively) + EPCS16 flash.

In both devices I have ROMs (megafunction), one in the master and two of them in the slave. All ROMs are initialized with .mif files.

The problem is: the slave ROMs are always broken, i.e. have bit errors, which can be seen in the In-system memory content editor (and also have bad CRC, which is calculated by the external CPU).

I can re-write content of ROM with ISMCE, and there are no errors then.

If slave is loaded from EPCS - there are errors.

If I try to reload slave via JTAG - there are errors.

 

I get no errors from quartus, not when programming EPCS, nor while JTAG operations. ROM megafunction themselves works correctly, i.e. I can read content of ROMs with external CPU with no problems, but content itself is broken.

 

Master is always working correctly - no errors, CRC is ok etc.

 

Connection is as shown in handbook, I also have 2 buffers on the DCLK and DATA[0] lines (74LVC1G125), but no series resistors (they are optional for 3.3V, according to handbook). Trace length from buffer to slave is about 110..120 mm.

Vic3Dexe_0-1655577406674.png

Appreciate for any help.

 

 

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1 Solution
Vic3Dexe
New Contributor I
160 Views

I think I've found the problem.

 

There is a trace connected to pin 76 on the master and pin 99 on the slave. Trace is pulled up to 3.3V via 2.2k

Vic3Dexe_0-1662160998444.png

This **bleep** resistor was dead, and the trace was actually floating.

I didn't use this pins before, so I can't reveal the resistor is dead.

As I start to use it, all logic became a total mess. Something worked, something not. By elimination I found the culprit.

 

I can't explain how this trace connected with loading errors (when FPGA not even in user mode), but the fact is - replacing resistor solved all problems, ROMs working now (though I don't use them anymore).

 

Thanks to all, problem solved!

View solution in original post

27 Replies
hareesh
Employee
152 Views

@Vic3Dexe wrote:   I've cut traces and placed series resistors afters buffers (51R)

 

those resistors where are you connecting (data line or clk line or on both lines)

  •  if you see bellow attachment  in schematic on clk and data lines using two different resistors in series.
Vic3Dexe
New Contributor I
141 Views

@hareesh wrote:

@Vic3Dexe wrote:   I've cut traces and placed series resistors afters buffers (51R)

 

those resistors where are you connecting (data line or clk line or on both lines)

  •  if you see bellow attachment  in schematic on clk and data lines using two different resistors in series.

As I said in post 4:

I've tried to remove buffers and change them to zero Ohm resistors - no changes.

Then I've replaced 0R resistors to 51R ones - no changes.

Then I've put buffers back, cut traces afters them (which are facing to the slave), and put 51R there in series. No changes.

 

So now it's like that. Both resistors placed as close as possible to buffers.

Vic3Dexe_0-1657978582320.png

There is no point in resistors before buffers, as the master working ok.

hareesh
Employee
131 Views

hi @Vic3Dexe ,

 

scope shot from oscilloscope is required. when can you share?

 

thanks,

Vic3Dexe
New Contributor I
123 Views

Awaiting access to my friend's oscilloscope (it's in use for now). Don't know when it will be avail. Maybe this week, maybe next.

hareesh
Employee
104 Views

Hi @Vic3Dexe,

 

Since there are no update from you. pls respond when can you share  oscilloscope data.

 

Thanks,

hareesh
Employee
87 Views

Hi,

Thanks for sharing files, just give me some time, we are working on it.


thanks,


Vic3Dexe
New Contributor I
161 Views

I think I've found the problem.

 

There is a trace connected to pin 76 on the master and pin 99 on the slave. Trace is pulled up to 3.3V via 2.2k

Vic3Dexe_0-1662160998444.png

This **bleep** resistor was dead, and the trace was actually floating.

I didn't use this pins before, so I can't reveal the resistor is dead.

As I start to use it, all logic became a total mess. Something worked, something not. By elimination I found the culprit.

 

I can't explain how this trace connected with loading errors (when FPGA not even in user mode), but the fact is - replacing resistor solved all problems, ROMs working now (though I don't use them anymore).

 

Thanks to all, problem solved!

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