Cyclone III user I/O stay LOW during JTAG configration

[Altera_Forum]

Hi,all 

I found all user I/Os became LOW during JTAG configruation in my situation. The device is Cyclone III 3C35. However, it is said that user I/Os must be tri-stated during JTAG configuration in Altera Configruation Handbook. Does something wrong with my configuration? Thanks a lot!

[Altera_Forum]

I never experienced a similar behaviour. The Cyclone III handbook states: 

  --- Quote Start ---  The user I/O pins and dual-purpose I/O pins have weak pull-up resistors which are always enabled (after POR) before and during configuration.  --- Quote End ---    I wonder, if there may be an option to cause a different behaviour through JTAG boundary scan instructions. But even if this would be the case, I can't imagine, that the Quartus Programmer uses other than known default settings.  Can it be, that external hardware is pulling-down the observed IOs?

[Altera_Forum]

Thanks to FvM! 

In fact, it is not true that ALL user I/O became LOW during JTAG configruation. This is due to my careless. Actually, only the AS configuration pin: ASDO, which is pin 6 of E144 package, became LOW during JTAG configruation. The others configruation pins and regular user I/O pins are tri-stated.   And, there isn't any external hardware which is pulling-down the ASDO pin. This pin is only LOW during JTAG configruation. After configruation, this pin act as a regular user I/O. I don't kown what's wrong with this pin?!   Regards   hustzq

[Altera_Forum]

Nothings's wrong I think.The said pin is dual pupose, in configuration state it's dedicated to AS interface. I would expect, that this behaviour is only present, when an AS configuration scheme is selected by MSEL pinstrapping, but I'm not sure about. It should be unaffeceted by Quartus device and pin options, that are only in effect in user mode.

[Altera_Forum]

Thanks to FvM! 

 I used Active Serial Standard scheme in my situation. However, I didn't see this phenomena on the platform of the Altera Cyclone 3 starter board, in which Cyclone 3c25 F324 is used. The starter board use AP scheme instead of AS scheme. May I guess that the phenomena can only exist in AS scheme?   Regards   hustzq

[Altera_Forum]

--- Quote Start ---  I didn't see this phenomena on the platform of the Altera Cyclone 3 starter board  --- Quote End ---  Yes that's what I expected, too. Dual purpose pins are acivated in configuration state according to MSEL.

[Altera_Forum]

But I still doubt why other dual purpose pins , such as DCLK, DATA0 and Flash_nCE, are tri-stated during JTAG configuration , and only ASDO pin is pull down. 

 In my project, the ASDO pin acts as an output request signal, which is active low. External hardware treat it as a request as soon as the pin become low. So wrong response would be caused if the pin become low during configuration. I am afraid that I must choose another pin instead of ASDO.   Regards,   hustzq

[Altera_Forum]

I don't know the reason for the specific behaviour. However, dual purpose pins must be expected to take arbitrary levels in configuration state respectively feed a signal. Thus they shouldn't be connected to hardware, that may show unintended reaction. If your design is using AS configuration, the problem arises during POR initial configuration anyway.