Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
19088 Discussions

Cyclone IV GPIO ,input in HDL, but leave float in hardware, must it set to week pull-up?

LChen23
Beginner
103 Views

Hi' 

an GPIO ,set it to input in HDL, but leave it floating in hardware,

I can sample it toggle in signalTAP if without week pull-up resistor. 

Why?

shoul all this kind of input pin be set to weekly pull-up ?

0 Kudos
2 Replies
AminT_Intel
Employee
91 Views

Hi,

 

I am not sure what exactly you are trying to do in your design. You can refer to these two sources on your design and let me know if you receive any errors:

1. Cyclone IV I/O Features: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-51006.pd...

2. Cyclone IV Device Datasheet: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-53001.pd...

3. Cyclone IV Device Handbook: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyclone4-hand...

 

Thanks

AminT_Intel
Employee
67 Views

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Reply